Patents by Inventor Alexandre Frey
Alexandre Frey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11269788Abstract: There is described a method of managing memory in an electronic device, the method comprising creating a set of equally sized logical regions in a logical address space, each logical region comprising a plurality of consecutive logical addresses, and mapping a subset of consecutive logical addresses within each logical region to a set of physical addresses within a corresponding physical memory region, the subset of consecutive logical addresses comprising the first logical address within the logical region, said first logical address being mapped to a base address within the corresponding physical memory region. Furthermore, there is described a controller for managing memory in an electronic device and a method of determining a physical memory address in a physical memory region using such a controller.Type: GrantFiled: August 18, 2020Date of Patent: March 8, 2022Assignee: NXP B.V.Inventors: Alexandre Frey, Ralf Malzahn, Frank Ernst Johannes Siedel, Shameer Puthalan, Andreas Lessiak, Daniel Kershaw
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Patent number: 11050726Abstract: A current operating system that is stored in a persistent storage circuit of a secure element is replaced by receiving a set of migration rules that specify changes to a set of data object types. Based upon the set of migration rules, a migration engine identifies data objects stored in a persistent storage circuit and corresponding to the set of data object types. For each of the identified data objects: a subset of the migration rules are selected that correspond to a data object type that corresponds to a particular data object, and based upon the selected subset, the particular data object is transformed. A new operating system can then be enabled.Type: GrantFiled: April 4, 2016Date of Patent: June 29, 2021Assignee: NXP B.V.Inventors: Andreas Lessiak, Josef Fruehwirth, Jozsef Jelenka, Harald Schlatte-Schatte, Alexandre Frey
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Publication number: 20210081335Abstract: There is described a method of managing memory in an electronic device, the method comprising creating a set of equally sized logical regions in a logical address space, each logical region comprising a plurality of consecutive logical addresses, and mapping a subset of consecutive logical addresses within each logical region to a set of physical addresses within a corresponding physical memory region, the subset of consecutive logical addresses comprising the first logical address within the logical region, said first logical address being mapped to a base address within the corresponding physical memory region. Furthermore, there is described a controller for managing memory in an electronic device and a method of determining a physical memory address in a physical memory region using such a controller.Type: ApplicationFiled: August 18, 2020Publication date: March 18, 2021Inventors: Alexandre Frey, Ralf Malzahn, Frank Ernst Johannes Siedel, Shameer Puthalan, Andreas Lessiak, Daniel Kershaw
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Patent number: 10789075Abstract: Various embodiments relate to a method and apparatus for embedding an operating system in a smart card product, which is certified and which derives multiple variants from the operating system, the method including the steps of certifying, a target of evaluation, the target of evaluation including an OS core mask and a plurality of components which includes OS components and plugin placeholders, building, by an image builder tool, romized content and runtime content including at least one of the plurality of components and customizing which of the plurality of components to include on the smart card product.Type: GrantFiled: September 29, 2017Date of Patent: September 29, 2020Assignee: NXP B.V.Inventors: Alexandre Frey, Josef Fruehwirth, Andreas Lessiak
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Publication number: 20190102205Abstract: Various embodiments relate to a method and apparatus for embedding an operating system in a smart card product, which is certified and which derives multiple variants from the operating system, the method including the steps of certifying, a target of evaluation, the target of evaluation including an OS core mask and a plurality of components which includes OS components and plugin placeholders, building, by an image builder tool, romized content and runtime content including at least one of the plurality of components and customizing which of the plurality of components to include on the smart card product.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Inventors: Alexandre FREY, Josef FRUEHWIRTH, Andreas LESSIAK
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Publication number: 20170289115Abstract: A current operating system that is stored in a persistent storage circuit of a secure element is replaced by receiving a set of migration rules that specify changes to a set of data object types. Based upon the set of migration rules, a migration engine identifies data objects stored in a persistent storage circuit and corresponding to the set of data object types. For each of the identified data objects: a subset of the migration rules are selected that correspond to a data object type that corresponds to a particular data object, and based upon the selected subset, the particular data object is transformed. A new operating system can then be enabled.Type: ApplicationFiled: April 4, 2016Publication date: October 5, 2017Inventors: Andreas Lessiak, Josef Fruehwirth, Jozsef Jelenka, Harald Schlatte - Schatte, Alexandre Frey
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Patent number: 8880904Abstract: The invention relates to a system and method for making data secure. The inventive system is characterized in that it comprises:—a monotonic counter;—a computational entity;—a physical data medium comprising one or a plurality of data blocks, a first master block comprising the last value recovered from the monotonic counter, an identifier of the last data block written on said medium, a first authentication code guaranteeing the authenticity of the written data block or blocks, a second authentication code calculated from the last written data block, said data being fixed at a neutral value, and a third authentication code guaranteeing the authenticity of the first master block, and a second master block forming a replica of the first master block; and—an authentication key. The invention is used, in particular, to make data secure against playback and sudden interruptions in service in embedded systems.Type: GrantFiled: September 27, 2007Date of Patent: November 4, 2014Assignee: Trusted Logic MobilityInventors: Axelle Apvrille, Alexandre Frey, Christophe Colas
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Patent number: 8719580Abstract: (EN)An electronic system (1) comprises a trusted processor (2), a trusted cache memory (3) and a mass storage memory (4). The data are stored in the mass storage memory (4), where the memories are divided into blocks, each block is identified by an address and the data are addressed via a verification tree. The verification tree is a tree structure comprising nodes where descendent nodes are attached to a root node and each node stores the address of the block containing each of its child nodes and a digest value of each block. A method for the verification of the data of such an electronic system comprises access to searched data at the same time reporting the corruption of data if a calculated digest is different from the current digest value.Type: GrantFiled: June 22, 2010Date of Patent: May 6, 2014Assignee: Trusted LogicInventors: Alexandre Frey, Gilles Peskine
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Patent number: 8588415Abstract: A method of securing a telecommunication terminal that is connected to a module used to identify a user of the terminal is described. The method includes a step including executing a procedure in which the terminal is matched to the identification module, consisting in: securely loading a first software program including a data matching key onto the identification module; securely loading a second software program which can operate in conjunction with the first software program onto the telecommunication terminal; transmitting a data matching key that corresponds to that of the first software program to the second software program; storing the transmitted data matching key in the secured storage zone of the telecommunication terminal; and conditionally submitting every response from the first software program to a request from the second software program upon verification at the true value of the valid possession of the data matching key by the second program.Type: GrantFiled: November 2, 2005Date of Patent: November 19, 2013Assignees: France Telecom, Trusted LogicInventors: Jean-Claude Pailles, Fabien Venries, Guillaume Bruyere, Alexandre Frey
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Publication number: 20120110336Abstract: (EN)An electronic system (1) comprises a trusted processor (2), a trusted cache memory (3) and a mass storage memory (4). The data are stored in the mass storage memory (4), where the memories are divided into blocks, each block is identified by an address and the data are addressed via a verification tree. The verification tree is a tree structure comprising nodes where descendent nodes are attached to a root node and each node stores the address of the block containing each of its child nodes and a digest value of each block. A method for the verification of the data of such an electronic system comprises access to searched data at the same time reporting the corruption of data if a calculated digest is different from the current digest value.Type: ApplicationFiled: June 22, 2010Publication date: May 3, 2012Applicant: TRUSTED LOGICInventors: Alexandre Frey, Gilles Peskine
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Patent number: 8082450Abstract: According to the inventive method, the chip card, a counting function (FC), a counter (Cpt) and a private key (Cf) stored in the write-only part of the memory region are stored in a persistent memory, the counter and the private key (Cf) being accessible only by the counting function (FC). When the chip card receives a counter request emitted by an requesting entity (ER), the counting function (FC) performs a modification of the counter (Cpt) and a calculation of a signature, and sends a response to the applicant entity (ER). When the on-board system receives the response to the counter request, the signature contained in the response is checked.Type: GrantFiled: December 14, 2006Date of Patent: December 20, 2011Assignee: Trusted LogicInventors: Alexandre Frey, Dominique Bolignano, Axelle Apvrille
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Publication number: 20110162083Abstract: The invention relates to a system and method for making data secure. The inventive system is characterized in that it comprises:—a monotonic counter;—a computational entity;—a physical data medium comprising one or a plurality of data blocks, a first master block comprising the last value recovered from the monotonic counter, an identifier of the last data block written on said medium, a first authentication code guaranteeing the authenticity of the written data block or blocks, a second authentication code calculated from the last written data block, said data being fixed at a neutral value, and a third authentication code guaranteeing the authenticity of the first master block, and a second master block forming a replica of the first master block; and—an authentication key. The invention is used, in particular, to make data secure against playback and sudden interruptions in service in embedded systems.Type: ApplicationFiled: September 27, 2007Publication date: June 30, 2011Applicant: TRUSTED LOGICInventors: Axelle Apvrille, Alexandre Frey, Christophe Colas
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Patent number: 7865724Abstract: The invention relates to a user interface-equipped computing device comprising means for implementing a series of applications, said means including two execution spaces. According to the invention, the applications of the second execution space (100, P1, 200, P2) have a level of security specifically higher than that of the applications of the first execution space (100, P1, 200, P2), said two execution spaces being hosted by a physical processing means which is designed such that it cannot be separated into two parts without destroying the physical processing means.Type: GrantFiled: December 17, 2004Date of Patent: January 4, 2011Assignees: France Telecom, Trusted LogicInventors: Cuihtlauac Alvarado, Jean-Bernard Blanchet, Laurent Frerebeau, Alexandre Frey, Eric Vetillard, Geoffroy Montel, Matthieu Maupetit
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Patent number: 7565646Abstract: A method for compressing an interpreted object code in a system using an interpreter, by identifying, in the interpreted object-coded program, similar non-contiguous groups of instructions, of arbitrarily complex structure, by replacing all or part of said groups in the interpreted object code of the program with newly-created specialized instructions and by instrumenting the interpreter and/or the interpreted object code of the program so as to render it capable of implementing the newly-created instructions.Type: GrantFiled: July 23, 2002Date of Patent: July 21, 2009Assignee: Trusted LogicInventors: Daniel Le Metayer, Renaud Marlet, Arnaud Venet, Alexandre Frey
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Publication number: 20090165148Abstract: The invention relates to a method for authenticating applications of a computer system including: a microprocessor, a plurality of applications, a general operating system (OS2) which can execute and manage the applications and which can associate each application identifier (3) with the identification information required for the execution thereof, and a trusted environment (EC) which offers services to said applications. According to the invention, before the services of the trusted environment (EC) can be accessed by an application, a hashing operation is performed on the identification information of said application and the trusted environment (EC) checks the authenticity of the result of the hashing operation.Type: ApplicationFiled: December 22, 2006Publication date: June 25, 2009Inventors: Alexandre Frey, Axelle Apvrille
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Publication number: 20080320315Abstract: According to the inventive method, the chip card, a counting function (FC), a counter (Cpt) and a private key (Cf) stored in the write-only part of the memory region are stored in a persistent memory, the counter and the private key (Cf) being accessible only by the counting function (FC). When the chip card receives a counter request emitted by an requesting entity (ER), the counting function (FC) performs a modification of the counter (Cpt) and a calculation of a signature, and sends a response to the applicant entity (ER). When the on-board system receives the response to the counter request, the signature contained in the response is checked.Type: ApplicationFiled: December 14, 2006Publication date: December 25, 2008Applicant: TRUSTED LOGICInventors: Alexandre Frey, Dominique Bolignano, Axelle Apvrille
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Patent number: 7467376Abstract: The invention concerns a method for compressing program code for execution in a system with few physical resources. This method comprises a semantic analysis of the code as to identify the objects accessed at each program point and to replace in this program groups of instructions used to access the objects by more compact specialised instructions.Type: GrantFiled: July 22, 2002Date of Patent: December 16, 2008Assignee: Trusted LogicInventors: Daniel Le Metayer, Renaud Marlet, Arnaud Venet, Alexandre Frey
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Publication number: 20080032668Abstract: The inventLion relates to a user interface-equppedi computing device comprising mneans for implementing a series of applicatiorm, said means including two execution spaces. According to the invention. the applications of the second execution space (100, P1, 200, P2) have a level of security specifically htigher than that of the applications of the first execution space (100, P1, 200, P2), said two execution spaces beino hosted by a physical processing means which is designed such that it carnnot be separated into two parts without destroying the physical processing means.Type: ApplicationFiled: December 17, 2004Publication date: February 7, 2008Inventors: Cuihtlauac Alvarado, Jean-Bernard Blanchet, Laurent Frerebeau, Alexandre Frey, Eric Vetillard, Geoffroy Montel, Matthieu Maupetit
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Publication number: 20070283361Abstract: Method for sharing the execution time of a physical processor (1) between at least two computer programs, the processor including a specific execution mode, referred to as the secure mode, having exclusive access to specific resources (3, 8, 9), and a first computer program, referred to as secure program, being executed exclusively in the secure execution mode, and a second computer program, referred to as non-secure program, being executed in an execution mode other than the secure execution mode, is characterized in that it includes the following steps: a) a periodic and regular cycle is defined for execution of the computer programs by the processor, b) the cycle is divided into two portions, one for executing the secure program, the other for executing the non-secure program.Type: ApplicationFiled: July 4, 2005Publication date: December 6, 2007Inventors: Jean-Bernard Blanchet, Alexandre Frey
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Patent number: 6901459Abstract: An existing active base logic flow between a master transceiver and a slave transceiver, is selected as reference logic flow wherein is generated a set of concurrent logic flows. The concurrent logic flows are built with successive elementary packets segmenting pairs of command/response. An exchange of pairs of command/response is initialised and continued by the master transceiver on the basis of specific commands. The slave transceiver triggers a segmentation by transmitting specific responses on the reference logic flow.Type: GrantFiled: October 17, 2001Date of Patent: May 31, 2005Assignee: Trusted LogicInventors: Alexandre Frey, Cédric Mesnil