Patents by Inventor Alexandre Y. Solomatnikov
Alexandre Y. Solomatnikov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9952972Abstract: Loading data from a computer memory system is disclosed. A memory system is provided, wherein some or all data stored in the memory system is organized as one or more pointer-linked data structures. One or more iterator registers are provided. A first pointer chain is loaded, having two or more pointers leading to a first element of a selected pointer-linked data structure to a selected iterator register. A second pointer chain is loaded, having two or more pointers leading to a second element of the selected pointer-linked data structure to the selected iterator register. The loading of the second pointer chain reuses portions of the first pointer chain that are common with the second pointer chain. Modifying data stored in a computer memory system is disclosed. A memory system is provided. One or more iterator registers are provided, wherein the iterator registers each include two or more pointer fields for storing two or more pointers that form a pointer chain leading to a data element.Type: GrantFiled: February 27, 2017Date of Patent: April 24, 2018Assignee: Intel CorporationInventors: David R. Cheriton, Amin Firoozshahian, Alexandre Y. Solomatnikov
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Patent number: 9870824Abstract: Loading data from a computer memory system is disclosed. A memory system is provided, wherein some or all data stored in the memory system is organized as one or more pointer-linked data structures. One or more iterator registers are provided. A first pointer chain is loaded, having two or more pointers leading to a first element of a selected pointer-linked data structure to a selected iterator register. A second pointer chain is loaded, having two or more pointers leading to a second element of the selected pointer-linked data structure to the selected iterator register. The loading of the second pointer chain reuses portions of the first pointer chain that are common with the second pointer chain. Modifying data stored in a computer memory system is disclosed. A memory system is provided. One or more iterator registers are provided, wherein the iterator registers each include two or more pointer fields for storing two or more pointers that form a pointer chain leading to a data element.Type: GrantFiled: March 16, 2017Date of Patent: January 16, 2018Assignee: Intel CorporationInventors: David R. Cheriton, Amin Firoozshahian, Alexandre Y. Solomatnikov
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Publication number: 20180004668Abstract: A searchable hot content cache stores frequently accessed data values in accordance with embodiments. In one embodiment, a circuit includes interface circuitry to receive memory requests from a processor. The circuit includes hardware logic to determine that a number of the memory requests that is to access a value meets or exceeds a threshold. The circuit includes a storage array to store the value in an entry based on a determination that the number meets or exceeds the threshold. In response to receipt of a memory request from the processor to access the same value at a memory address, the hardware logic is to map the memory address to the entry of the storage array.Type: ApplicationFiled: June 30, 2016Publication date: January 4, 2018Inventors: Omid J. AZIZI, Alexandre Y. SOLOMATNIKOV, Amin FIROOZSHAHIAN, John P. STEVENSON, Mahesh MADDURY
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Publication number: 20170249992Abstract: Loading data from a computer memory system is disclosed. A memory system is provided, wherein some or all data stored in the memory system is organized as one or more pointer-linked data structures. One or more iterator registers are provided. A first pointer chain is loaded, having two or more pointers leading to a first element of a selected pointer-linked data structure to a selected iterator register. A second pointer chain is loaded, having two or more pointers leading to a second element of the selected pointer-linked data structure to the selected iterator register. The loading of the second pointer chain reuses portions of the first pointer chain that are common with the second pointer chain. Modifying data stored in a computer memory system is disclosed. A memory system is provided. One or more iterator registers are provided, wherein the iterator registers each include two or more pointer fields for storing two or more pointers that form a pointer chain leading to a data element.Type: ApplicationFiled: March 16, 2017Publication date: August 31, 2017Inventors: DAVID R. CHERITON, AMIN FIROOZSHAHIAN, ALEXANDRE Y. SOLOMATNIKOV
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Publication number: 20170168938Abstract: Loading data from a computer memory system is disclosed. A memory system is provided, wherein some or all data stored in the memory system is organized as one or more pointer-linked data structures. One or more iterator registers are provided. A first pointer chain is loaded, having two or more pointers leading to a first element of a selected pointer-linked data structure to a selected iterator register. A second pointer chain is loaded, having two or more pointers leading to a second element of the selected pointer-linked data structure to the selected iterator register. The loading of the second pointer chain reuses portions of the first pointer chain that are common with the second pointer chain. Modifying data stored in a computer memory system is disclosed. A memory system is provided. One or more iterator registers are provided, wherein the iterator registers each include two or more pointer fields for storing two or more pointers that form a pointer chain leading to a data element.Type: ApplicationFiled: February 27, 2017Publication date: June 15, 2017Inventors: DAVID R. CHERITON, AMIN FIROOZSHAHIAN, ALEXANDRE Y. SOLOMATNIKOV
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Patent number: 9601199Abstract: Loading data from a computer memory system is disclosed. A memory system is provided, wherein some or all data stored in the memory system is organized as one or more pointer-linked data structures. One or more iterator registers are provided. A first pointer chain is loaded, having two or more pointers leading to a first element of a selected pointer-linked data structure to a selected iterator register. A second pointer chain is loaded, having two or more pointers leading to a second element of the selected pointer-linked data structure to the selected iterator register. The loading of the second pointer chain reuses portions of the first pointer chain that are common with the second pointer chain. Modifying data stored in a computer memory system is disclosed. A memory system is provided. One or more iterator registers are provided, wherein the iterator registers each include two or more pointer fields for storing two or more pointers that form a pointer chain leading to a data element.Type: GrantFiled: July 23, 2010Date of Patent: March 21, 2017Assignee: Intel CorporationInventors: David R. Cheriton, Amin Firoozshahian, Alexandre Y. Solomatnikov
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Publication number: 20160224261Abstract: A memory controller is used to receive a first request for a portion of a physical memory and metadata associated with the portion of the physical memory. The first request for the portion of the physical memory is translated to correspond to an indirect data structure. The indirect data structure comprises a reference to a data line, and a metadata associated with the data line. The data line is formed within the physical memory.Type: ApplicationFiled: October 11, 2015Publication date: August 4, 2016Applicant: Intel CorporationInventors: David R. Cheriton, Alexandre Y. Solomatnikov
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Patent number: 8504791Abstract: Intercepting a requested memory operation corresponding to a conventional memory is disclosed. The requested memory operation is translated to be applied to a structured memory.Type: GrantFiled: September 27, 2012Date of Patent: August 6, 2013Assignee: Hicamp Systems, Inc.Inventors: David R. Cheriton, Alexandre Y. Solomatnikov
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Patent number: 8407428Abstract: Intercepting a requested memory operation corresponding to a conventional memory is disclosed. The requested memory operation is translated to be applied to a structured memory.Type: GrantFiled: May 20, 2010Date of Patent: March 26, 2013Assignee: Hicamp Systems, Inc.Inventors: David R. Cheriton, Alexandre Y. Solomatnikov
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Publication number: 20130024645Abstract: Intercepting a requested memory operation corresponding to a conventional memory is disclosed. The requested memory operation is translated to be applied to a structured memory.Type: ApplicationFiled: May 20, 2010Publication date: January 24, 2013Applicant: HICAMP SYSTEMS, INC.Inventors: David R. Cheriton, Alexandre Y. Solomatnikov
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Publication number: 20110010347Abstract: Loading data from a computer memory system is disclosed. A memory system is provided, wherein some or all data stored in the memory system is organized as one or more pointer-linked data structures. One or more iterator registers are provided. A first pointer chain is loaded, having two or more pointers leading to a first element of a selected pointer-linked data structure to a selected iterator register. A second pointer chain is loaded, having two or more pointers leading to a second element of the selected pointer-linked data structure to the selected iterator register. The loading of the second pointer chain reuses portions of the first pointer chain that are common with the second pointer chain. Modifying data stored in a computer memory system is disclosed. A memory system is provided. One or more iterator registers are provided, wherein the iterator registers each include two or more pointer fields for storing two or more pointers that form a pointer chain leading to a data element.Type: ApplicationFiled: July 23, 2010Publication date: January 13, 2011Applicant: Hicamp Systems, Inc.Inventors: David R. Cheriton, Amin Firoozshahian, Alexandre Y. Solomatnikov