Abstract: Methods, systems, and devices for clock domain crossing queue are described. A memory sub-system can generate a namespace map having a set of namespace blocks associated with a memory sub-system. The namespace blocks can include one or more logical block addresses associated with the memory sub-system. One namespace block of the set of namespace blocks can include an indication that can indicate that the namespace block and each namespace block following the namespace block are available for mapping. The memory sub-system can receive a request to create a namespace and sequentially map one or more available namespace blocks to the namespace according to the ordering of the namespace map, including the namespace block with the indication.

Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory (e.g., NAND flash memory of a solid-state drive) is allocated to a namespace for use by a host device. Master boot record (MBR) data is written by a controller of the memory to an MBR region assigned to the namespace. Read circuitry is configured to read either of user data or MBR data in response to read commands received from the host device for addresses in the namespace. The user data or the MBR data is read using a regular read operation of the controller (e.g., without triggering any hardware exceptions that require significantly slower processing by firmware of the controller).

Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory has a namespace formatted using a first sector size. Master boot record (MBR) data is written to an MBR region outside of the namespace using the first sector size. After writing the MBR data, the namespace is reformatted using a second sector size. A read command is received from a host for an address in an MBR address range of the namespace. In response to receiving the read command, the MBR data is read from the MBR region. Padding is added to the read MBR data, and the padded MBR data is sent to the host device.

Abstract: Methods, systems, and devices for clock domain crossing queue are described. A memory sub-system can generate a namespace map having a set of namespace blocks associated with a memory sub-system. The namespace blocks can include one or more logical block addresses associated with the memory sub-system. One namespace block of the set of namespace blocks can include an indication that can indicate that the namespace block and each namespace block following the namespace block are available for mapping. The memory sub-system can receive a request to create a namespace and sequentially map one or more available namespace blocks to the namespace according to the ordering of the namespace map, including the namespace block with the indication.

Abstract: Methods, systems, and devices for clock domain crossing queue are described. A memory sub-system can generate a namespace map having a set of namespace blocks associated with a memory sub-system. The namespace blocks can include one or more logical block addresses associated with the memory sub-system. One namespace block of the set of namespace blocks can include an indication that can indicate that the namespace block and each namespace block following the namespace block are available for mapping. The memory sub-system can receive a request to create a namespace and sequentially map one or more available namespace blocks to the namespace according to the ordering of the namespace map, including the namespace block with the indication.

Abstract: A computing system includes: a volatile memory configured to: store a debug assert flag mask including bits; cores, coupled to the volatile memory, configured to: detect an error in at least one of the cores, set at least one of the bits corresponding to the cores with the error detected, collect debug information for each of the cores with the error detected, collect operating information for each of the cores without the error detected, generate assert dump information based on compiling the debug information; and a nonvolatile memory, coupled to at least one of the cores, configured to: store the assert dump information, the operating information, configured to by at least one of the cores.

Abstract: A computing system includes: a volatile memory configured to: store a debug assert flag mask including bits; cores, coupled to the volatile memory, configured to: detect an error in at least one of the cores, set at least one of the bits corresponding to the cores with the error detected, collect debug information for each of the cores with the error detected, collect operating information for each of the cores without the error detected, generate assert dump information based on compiling the debug information; and a nonvolatile memory, coupled to at least one of the cores, configured to: store the assert dump information, the operating information, configured to by at least one of the cores.