Patents by Inventor Alexis BOUTILLER
Alexis BOUTILLER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11416352Abstract: A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.Type: GrantFiled: November 15, 2019Date of Patent: August 16, 2022Assignee: ARTERIS, INC.Inventors: Jean Philippe Loison, Benoit de Lescure, Alexis Boutiller, Rohit Bansal, Parimal Gaikwad, Mohammed Khaleeluddin
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Patent number: 11176297Abstract: A resilient system implementation in a network-on-ship with at least one functional logic unit and at least one duplicated logic unit. A resilient system and method, in accordance with the invention, are disclosed for detecting a fault or an uncorrectable error and isolating the fault. Isolation of the fault prevents further propagation of the fault throughout the system. The resilient system includes isolation logic or an isolation unit that isolates the fault.Type: GrantFiled: February 25, 2020Date of Patent: November 16, 2021Assignee: ARTERIS, INC.Inventors: Alexis Boutiller, Benoit de Lescure
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Patent number: 10902166Abstract: A resilient system implementation in a network-on-ship with at least one functional logic unit and at least one duplicated logic unit. A resilient system and method, in accordance with the invention, are disclosed for detecting a fault or an uncorrectable error and isolating the fault. Isolation of the fault prevents further propagation of the fault throughout the system. The resilient system includes isolation logic or an isolation unit that isolates the fault.Type: GrantFiled: December 13, 2018Date of Patent: January 26, 2021Assignee: ARTERIS, INC.Inventors: Benoit de Lescure, Alexis Boutiller
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Publication number: 20200193077Abstract: A resilient system implementation in a network-on-ship with at least one functional logic unit and at least one duplicated logic unit. A resilient system and method, in accordance with the invention, are disclosed for detecting a fault or an uncorrectable error and isolating the fault. Isolation of the fault prevents further propagation of the fault throughout the system. The resilient system includes isolation logic or an isolation unit that isolates the fault.Type: ApplicationFiled: February 25, 2020Publication date: June 18, 2020Applicant: ARTERIS, INC.Inventors: Alexis BOUTILLER, Benoit de LESCURE
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Publication number: 20200159631Abstract: A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents.Type: ApplicationFiled: November 15, 2019Publication date: May 21, 2020Applicant: ARTERIS, INC.Inventors: Jean Philippe Loison, Benoit deLESCURE, Alexis BOUTILLER, Rohit BANSAL, Parimal GAIKWAD
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Patent number: 10592358Abstract: A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.Type: GrantFiled: December 27, 2016Date of Patent: March 17, 2020Assignee: ARTERIS, INC.Inventors: Benoit deLescure, Jean Philippe Loison, Alexis Boutiller, Rohit Bansal, Parimal Gaikwad
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Patent number: 10452499Abstract: A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.Type: GrantFiled: July 16, 2018Date of Patent: October 22, 2019Assignee: ARTERIS, INC.Inventors: Benoit de Lescure, Jean Philippe Loison, Alexis Boutiller
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Publication number: 20190205489Abstract: A resilient system implementation in a network-on-ship with at least one functional logic unit and at least one duplicated logic unit. A resilient system and method, in accordance with the invention, are disclosed for detecting a fault or an uncorrectable error and isolating the fault. Isolation of the fault prevents further propagation of the fault throughout the system. The resilient system includes isolation logic or an isolation unit that isolates the fault.Type: ApplicationFiled: December 13, 2018Publication date: July 4, 2019Applicant: Arteris, Inc.Inventors: Benoit de LESCURE, Alexis BOUTILLER
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Publication number: 20180322021Abstract: A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents.Type: ApplicationFiled: July 16, 2018Publication date: November 8, 2018Applicant: Arteris, Inc.Inventors: Benoit de LESCURE, Jean Philippe LOISON, Alexis BOUTILLER
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Patent number: 10025677Abstract: A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.Type: GrantFiled: December 21, 2016Date of Patent: July 17, 2018Assignee: ARTERIS, Inc.Inventors: Benoit de Lescure, Jean Philippe Loison, Alexis Boutiller
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Publication number: 20180173597Abstract: A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents.Type: ApplicationFiled: December 21, 2016Publication date: June 21, 2018Applicant: Arteris, Inc.Inventors: Benoit de LESCURE, Jean Philippe LOISON, Alexis BOUTILLER
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Publication number: 20180157545Abstract: A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents.Type: ApplicationFiled: December 27, 2016Publication date: June 7, 2018Applicant: Arteris, Inc.Inventors: Benoit deLESCURE, Jean Philippe LOISON, Alexis BOUTILLER, Rohit BANSAL, Parimal GAIKWAD