Abstract: A cache memory structure comprises a cache memory that has a plurality of ports for reading data from the cache memory and a plurality of ports for writing data into the cache memory. A switching network matrix having controllable switch elements for connecting of the cache memory ports to bus terminals is arranged between the bus terminals and processors, to an instruction unit of a processor, to a main memory, and to the cache memory. The switch elements of the switching network matrix are controlled by a cache memory controller such that the bus terminals can be selectively connected to the write or read ports of the cache memory. With the assistance of the switching network matrix, it becomes possible to select the number of ports of the cache memory to be less than the plurality of bus terminals that access the cache memory.