Abstract: A flip chip device and methods for fabrication are provided. An interconnect layer for a device include a plurality of solder bumps arranged within the interconnect layer. A first subset of the plurality of solder bumps has a first cross-sectional area, where the first subset is arranged along a first position at a first edge of the interconnect layer. A second subset of the plurality of solder bumps has a second cross-sectional area, where the second subset is arranged at a second position of the interconnect layer. A third subset of the plurality of solder bumps is arranged between the first position and the second position, where the third subset has a plurality of cross-sectional areas.

Abstract: A deposition apparatus for depositing a material on a substrate is provided. The deposition apparatus has a processing chamber defining a processing space in which the substrate is arranged, an ultraviolet radiation assembly configured to emit ultraviolet radiation and a microwave radiation assembly configured to emit microwave radiation into an excitation space that can be the same as the processing space, and a gas feed assembly configured to feed a precursor gas into the processing space and a reactive gas into the excitation space. The ultraviolet radiation assembly and the microwave radiation assembly are operated in combination to excite the reactive gas in the excitation space. The material is deposited on the substrate from the reaction of the excited reactive gas and the precursor gas. A method for using the deposition apparatus to deposit a material on a substrate is provided.

Abstract: Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers.

Abstract: A deposition apparatus for depositing a material on a substrate is provided. The deposition apparatus has a processing chamber defining a processing space in which the substrate is arranged, an ultraviolet radiation assembly configured to emit ultraviolet radiation and a microwave radiation assembly configured to emit microwave radiation into an excitation space that can be the same as the processing space, and a gas feed assembly configured to feed a precursor gas into the processing space and a reactive gas into the excitation space. The ultraviolet radiation assembly and the microwave radiation assembly are operated in combination to excite the reactive gas in the excitation space. The material is deposited on the substrate from the reaction of the excited reactive gas and the precursor gas. A method for using the deposition apparatus to deposit a material on a substrate is provided.

Abstract: The present invention provides interconnects with self-forming wrap-all-around graphene barrier layer. In one aspect, a method of forming an interconnect structure is provided. The method includes: patterning at least one trench in a dielectric; forming an interconnect in the at least one trench embedded in the dielectric; and forming a wrap-all-around graphene barrier surrounding the interconnect. An interconnect structure having a wrap-all-around graphene barrier is also provided.

Abstract: The present invention provides interconnects with self-forming wrap-all-around graphene barrier layer. In one aspect, a method of forming an interconnect structure is provided. The method includes: patterning at least one trench in a dielectric; forming an interconnect in the at least one trench embedded in the dielectric; and forming a wrap-all-around graphene barrier surrounding the interconnect. An interconnect structure having a wrap-all-around graphene barrier is also provided.

Abstract: Integrated circuits including at least two electrically conductive interconnect lines and methods of manufacturing generally include a surface of the integrated circuit. At least two electrically conductive interconnect lines are separated by a space of less than 90 nm and are formed on the surface. Each of the at least two interconnect lines includes a metal cap, a copper conductor having an average grain size greater than a line width of the interconnect. A liner layer is provided, wherein the liner layer and the metal cap encapsulate the copper conductor. A dielectric layer overlaying the at least two electrically conductive interconnect lines and extending along sidewalls thereof is provided, wherein the dielectric layer is configured to provide an airgap between the at least two interconnect lines at the spacing.

Abstract: Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers.

Abstract: A deposition apparatus for depositing a material on a substrate is provided. The deposition apparatus has a processing chamber defining a processing space in which the substrate is arranged, an ultraviolet radiation assembly configured to emit ultraviolet radiation and a microwave radiation assembly configured to emit microwave radiation into an excitation space that can be the same as the processing space, and a gas feed assembly configured to feed a precursor gas into the processing space and a reactive gas into the excitation space. The ultraviolet radiation assembly and the microwave radiation assembly are operated in combination to excite the reactive gas in the excitation space. The material is deposited on the substrate from the reaction of the excited reactive gas and the precursor gas. A method for using the deposition apparatus to deposit a material on a substrate is provided.

Abstract: A deposition apparatus for depositing a material on a substrate is provided. The deposition apparatus has a processing chamber defining a processing space in which the substrate is arranged, an ultraviolet radiation assembly configured to emit ultraviolet radiation and a microwave radiation assembly configured to emit microwave radiation into an excitation space that can be the same as the processing space, and a gas feed assembly configured to feed a precursor gas into the processing space and a reactive gas into the excitation space. The ultraviolet radiation assembly and the microwave radiation assembly are operated in combination to excite the reactive gas in the excitation space. The material is deposited on the substrate from the reaction of the excited reactive gas and the precursor gas. A method for using the deposition apparatus to deposit a material on a substrate is provided.

Abstract: A deposition apparatus for depositing a material on a substrate is provided. The deposition apparatus has a processing chamber defining a processing space in which the substrate is arranged, an ultraviolet radiation assembly configured to emit ultraviolet radiation and a microwave radiation assembly configured to emit microwave radiation into an excitation space that can be the same as the processing space, and a gas feed assembly configured to feed a precursor gas into the processing space and a reactive gas into the excitation space. The ultraviolet radiation assembly and the microwave radiation assembly are operated in combination to excite the reactive gas in the excitation space. The material is deposited on the substrate from the reaction of the excited reactive gas and the precursor gas. A method for using the deposition apparatus to deposit a material on a substrate is provided.

Abstract: Integrated circuits including at least two electrically conductive interconnect lines and methods of manufacturing generally include a surface of the integrated circuit. At least two electrically conductive interconnect lines are separated by a space of less than 90 nm and are formed on the surface. Each of the at least two interconnect lines includes a metal cap, a copper conductor having an average grain size greater than a line width of the interconnect. A liner layer is provided, wherein the liner layer and the metal cap encapsulate the copper conductor. A dielectric layer overlaying the at least two electrically conductive interconnect lines and extending along sidewalls thereof is provided, wherein the dielectric layer is configured to provide an airgap between the at least two interconnect lines at the spacing.

Abstract: An electrical device including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting electrical current. A liner is present between the opening and the copper including structure. The liner includes a superlattice structure comprised of a metal oxide layer, a metal layer present on the metal oxide layer, and a metal nitride layer that is present on the metal layer. A first layer of the superlattice structure that is in direct contact with the low-k dielectric material is one of said metal oxide layer and a final layer of the superlattice structure that is in direct contact with the copper including structure is one of the metal nitride layers.

Abstract: Hall effect devices and field effect transistors are formed incorporating a carbon-based nanostructure layer such as carbon nanotubes and/or graphene with a sacrificial metal layer formed there over to protect the carbon-based nanostructure layer during processing.

Abstract: A substrate incorporating semiconductor regions electrically isolated by shallow trenches filled with hexagonal, textured or columnar boron nitride. A process for filling shallow trenches in a semiconductor substrate with columnar textured boron nitride using pulsed plasma enhanced chemical vapor deposition (Pulsed PECVD) and plasma assisted atomic layer deposition (PAALD).

Abstract: Hall effect devices and field effect transistors are formed incorporating a carbon-based nanostructure layer such as carbon nanotubes and/or graphene with a sacrificial metal layer formed there over to protect the carbon-based nanostructure layer during processing.

Abstract: An electrical device including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting electrical current. A liner is present between the opening and the copper including structure. The liner includes a superlattice structure comprised of a metal oxide layer, a metal layer present on the metal oxide layer, and a metal nitride layer that is present on the metal layer. A first layer of the superlattice structure that is in direct contact with the low-k dielectric material is one of said metal oxide layer and a final layer of the superlattice structure that is in direct contact with the copper including structure is one of the metal nitride layers.

Abstract: Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films.

Abstract: Embodiments of the present invention provide semiconductor structures and methods for making the same that include a boron nitride (BN) spacer on a gate stack, such as a gate stack of a planar FET or FinFET. The boron nitride spacer is fabricated using atomic layer deposition (ALD) and/or plasma enhanced atomic layer deposition (PEALD) techniques to produce a boron nitride spacer at relatively low temperatures that are conducive to devices made from materials such as silicon (Si), silicon germanium (SiGe), germanium (Ge), and/or III-V compounds. Furthermore, the boron nitride spacer may be fabricated to have various desirable properties, including a hexagonal textured structure.

Abstract: Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films.