Patents by Inventor Alfred Haimerl
Alfred Haimerl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10198684Abstract: A smart card module includes a substrate having a first main surface and a second main surface, which is opposite the first main surface. The substrate has a plurality of plated-through holes, which extend through the substrate from the first main surface to the second main surface. The smart card module further includes a chip over the first main surface of the substrate, a first metal structure over the second main surface of the substrate, electrically insulating material, which covers the first metal structure, and a second metal structure over the electrically insulating material, wherein the second metal structure is electrically insulated from the first metal structure by the electrically insulating material. The chip is connected to the first metal structure by at least one first plated-through hole. The chip is connected to the second metal structure by at least one second plated-through hole.Type: GrantFiled: May 22, 2015Date of Patent: February 5, 2019Assignee: Infineon Technologies AGInventors: Frank Pueschner, Alfred Haimerl, Jens Pohl, Wolfgang Schindler
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Patent number: 10128180Abstract: A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material.Type: GrantFiled: November 24, 2017Date of Patent: November 13, 2018Assignee: INFINEON TECHNOLOGIES AGInventors: Michael Bauer, Alfred Haimerl, Angela Kessler, Wolfgang Schober
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Publication number: 20180096924Abstract: A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material.Type: ApplicationFiled: November 24, 2017Publication date: April 5, 2018Inventors: Michael Bauer, Alfred Haimerl, Angela Kessler, Wolfgang Schober
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Patent number: 9859198Abstract: A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material.Type: GrantFiled: December 15, 2014Date of Patent: January 2, 2018Assignee: INFINEON TECHNOLOGIES AGInventors: Michael Bauer, Alfred Haimerl, Angela Kessler, Wolfgang Schober
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Patent number: 9633927Abstract: A chip arrangement includes semiconductor chips coupled to opposing sides of an insulating layer. The arrangement includes a first semiconductor chip having a first chip surface presenting a first chip conductive region. An electrically insulating layer includes a first layer surface presenting a first layer conductive region, and a second, opposing surface presenting a second layer conductive region. The electrically insulating layer is coupled to the first semiconductor chip by applying the first layer conductive region to the first chip conductive region. The electrically insulating layer is then coupled to the second chip conductive region by applying the second layer conductive region to the second chip conductive region.Type: GrantFiled: August 14, 2013Date of Patent: April 25, 2017Assignee: Infineon Technologies AGInventors: Joachim Mahler, Alfred Haimerl, Angela Kessler, Michael Bauer
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Publication number: 20150339565Abstract: A smart card module includes a substrate having a first main surface and a second main surface, which is opposite the first main surface. The substrate has a plurality of plated-through holes, which extend through the substrate from the first main surface to the second main surface. The smart card module further includes a chip over the first main surface of the substrate, a first metal structure over the second main surface of the substrate, electrically insulating material, which covers the first metal structure, and a second metal structure over the electrically insulating material, wherein the second metal structure is electrically insulated from the first metal structure by the electrically insulating material. The chip is connected to the first metal structure by at least one first plated-through hole. The chip is connected to the second metal structure by at least one second plated-through hole.Type: ApplicationFiled: May 22, 2015Publication date: November 26, 2015Inventors: Frank PUESCHNER, Alfred HAIMERL, Jens POHL, Wolfgang SCHINDLER
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Publication number: 20150097282Abstract: A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material.Type: ApplicationFiled: December 15, 2014Publication date: April 9, 2015Inventors: Michael Bauer, Alfred Haimerl, Angela Kessler, Wolfgang Schober
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Publication number: 20140001622Abstract: A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material.Type: ApplicationFiled: June 27, 2012Publication date: January 2, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Michael Bauer, Alfred Haimerl, Angela Kessler, Wolfgang Schober
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Publication number: 20130328206Abstract: A chip arrangement includes semiconductor chips coupled to opposing sides of an insulating layer. The arrangement includes a first semiconductor chip having a first chip surface presenting a first chip conductive region. An electrically insulating layer includes a first layer surface presenting a first layer conductive region, and a second, opposing surface presenting a second layer conductive region. The electrically insulating layer is coupled to the first semiconductor chip by applying the first layer conductive region to the first chip conductive region. The electrically insulating layer is then coupled to the second chip conductive region by applying the second layer conductive region to the second chip conductive region.Type: ApplicationFiled: August 14, 2013Publication date: December 12, 2013Applicant: Infineon Technologies AGInventors: Joachim Mahler, Alfred Haimerl, Angela Kessler, Michael Bauer
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Patent number: 8519547Abstract: A chip arrangement includes semiconductor chips coupled to opposing sides of an insulating layer. The arrangement includes a first semiconductor chip having a first chip surface presenting a first chip conductive region. An electrically insulating layer includes a first layer surface presenting a first layer conductive region, and a second, opposing surface presenting a second layer conductive region. The electrically insulating layer is coupled to the first semiconductor chip by applying the first layer conductive region to the first chip conductive region. The electrically insulating layer is then coupled to the second chip conductive region by applying the second layer conductive region to the second chip conductive region.Type: GrantFiled: March 6, 2012Date of Patent: August 27, 2013Assignee: Infineon Technologies AGInventors: Joachim Mahler, Alfred Haimerl, Angela Kessler, Michael Bauer
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Patent number: 8507080Abstract: Composite with a first part composed of a thermoset material and with a second part composed of a thermoplastic material, and with an adhesion-promoter layer located between these, where the first part has been bonded by way of the adhesion-promoter layer to the second part, and where the adhesion-promoter layer comprises pyrolytically deposited semiconductor oxides and/or pyrolytically deposited metal oxides.Type: GrantFiled: April 26, 2006Date of Patent: August 13, 2013Assignee: Infineon Technologies AGInventors: Joachim Mahler, Alfred Haimerl, Wolfgang Schober, Michael Bauer, Angela Kessler
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Patent number: 8440733Abstract: Semiconductor component and method for production of a semiconductor component. The invention relates to a semiconductor component having a semiconductor chip, which is arranged on a substrate, in one embodiment on a chip carrier, and an encapsulation material, which at least partially surrounds the semiconductor chip. The chip carrier is at least partly provided with a layer of polymer foam.Type: GrantFiled: May 1, 2012Date of Patent: May 14, 2013Assignee: Infineon Technologies AGInventors: Joachim Mahler, Alfred Haimerl, Michael Bauer, Angela Kessler, Wolfgang Schober
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Publication number: 20130062781Abstract: A chip arrangement includes semiconductor chips coupled to opposing sides of an insulating layer. The arrangement includes a first semiconductor chip having a first chip surface presenting a first chip conductive region. An electrically insulating layer includes a first layer surface presenting a first layer conductive region, and a second, opposing surface presenting a second layer conductive region. The electrically insulating layer is coupled to the first semiconductor chip by applying the first layer conductive region to the first chip conductive region. The electrically insulating layer is then coupled to the second chip conductive region by applying the second layer conductive region to the second chip conductive region.Type: ApplicationFiled: March 6, 2012Publication date: March 14, 2013Applicant: INFINEON TECHNOLOGIES AGInventors: Joachim Mahler, Alfred Haimerl, Michael Bauer
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Patent number: 8354299Abstract: A semiconductor component including a stack of semiconductor chips, the semiconductor chips being fixed cohesively one on top of another, is disclosed. The contact areas of the semiconductor chips are led as far as the edges of the semiconductor chips and conductor portions extend at least from an upper edge to a lower edge of the edge sides of the semiconductor chips in order to electrically connect the contact area of the stacked semiconductor chips to one another.Type: GrantFiled: February 9, 2005Date of Patent: January 15, 2013Assignee: Infineon Technologies AGInventors: Michael Bauer, Thomas Engling, Alfred Haimerl, Angela Kessler, Joachim Mahler, Wolfgang Schober
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Publication number: 20120223424Abstract: Semiconductor component and method for production of a semiconductor component. The invention relates to a semiconductor component having a semiconductor chip, which is arranged on a substrate, in one embodiment on a chip carrier, and an encapsulation material, which at least partially surrounds the semiconductor chip. The chip carrier is at least partly provided with a layer of polymer foam.Type: ApplicationFiled: May 1, 2012Publication date: September 6, 2012Applicant: Infineon Technologies AGInventors: Joachim Mahler, Alfred Haimerl, Michael Bauer, Angela Kessler, Wolfgang Schober
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Patent number: 8178390Abstract: A semiconductor component is disclosed. In one embodiment, the semiconductor component includes a semiconductor chip, which is arranged on a substrate, and a housing, which at least partially surrounds the semiconductor chip. The substrate is at least partly provided with a layer of polymer foam.Type: GrantFiled: February 20, 2006Date of Patent: May 15, 2012Assignee: Infineon Technologies AGInventors: Joachim Mahler, Alfred Haimerl, Michael Bauer, Angela Kessler, Wolfgang Schober
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Patent number: 8129831Abstract: A chip arrangement includes semiconductor chips coupled to opposing sides of an insulating layer. The arrangement includes a first semiconductor chip having a first chip surface presenting a first chip conductive region. An electrically insulating layer includes a first layer surface presenting a first layer conductive region, and a second, opposing surface presenting a second layer conductive region. The electrically insulating layer is coupled to the first semiconductor chip by applying the first layer conductive region to the first chip conductive region. The electrically insulating layer is then coupled to the second chip conductive region by applying the second layer conductive region to the second chip conductive region.Type: GrantFiled: February 16, 2007Date of Patent: March 6, 2012Assignee: Infineon Technologies AGInventors: Joachim Mahler, Alfred Haimerl, Michael Bauer
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Patent number: 8017438Abstract: A semiconductor module includes a module package including a first substrate having a first semiconductor device and a second substrate having a second semiconductor device. A first outer conductor extends from the module package and is connected to the first substrate and a second outer conductor extends from the module package and is connected to the second substrate. A method for producing the semiconductor module includes attaching first outer conductors of a leadframe to a first substrate, where the first substrate includes a first semiconductor device that is attached to the first substrate either before or after attaching the first outer conductors. A second substrate is provided including a signal processing circuit and the second substrate is fastening to second outer conductors of the leadframe.Type: GrantFiled: December 19, 2006Date of Patent: September 13, 2011Assignee: Infineon Technologies AGInventors: Michael Bauer, Angela Kessler, Wolfgang Schober, Alfred Haimerl, Joachim Mahler
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Patent number: 8013441Abstract: One aspect of the invention relates to a power semiconductor device in lead frame technology and a method for producing the same. The power semiconductor device has a vertical current path through a power semiconductor chip. The power semiconductor chip has at least one large-area electrode on its top side and a large-area electrode on its rear side. The rear side electrode is surface-mounted on a lead frame chip island of a lead frame and the top side electrode is electrically connected to an internal lead of the lead frame via a connecting element. The connecting element has an electrically conductive film on a surface facing the top side electrode, the electrically conductive film extending from the top side electrode to the internal lead.Type: GrantFiled: October 16, 2006Date of Patent: September 6, 2011Assignee: Infineon Technologies AGInventors: Michael Bauer, Alfred Haimerl, Angela Kessler, Joachim Mahler, Wolfgang Schober
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Patent number: 7911039Abstract: A component arrangement comprising a carrier, a component in a housing with electrical contacts and a moulding compound that encloses the carrier, the semiconductor component in the housing and the electrical contacts, wherein the component is applied on the carrier, and wherein the carrier is provided with holes, and a method for producing a component arrangement, wherein the carrier is provided with holes, the component is positioned on the carrier, the component is connected to the carrier, the component with the carrier is positioned in the leadframe, and this arrangement is enclosed by a moulding compound.Type: GrantFiled: September 25, 2007Date of Patent: March 22, 2011Assignee: Infineon Technologies AGInventors: Michael Bauer, Alfred Haimerl, Angela Kessler, Joachim Mahler, Wolfgang Schober