Patents by Inventor Ali Feiz Zarrin Ghalam
Ali Feiz Zarrin Ghalam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190295614Abstract: A wave pipeline includes a first stage, a plurality of second stages, and a third stage. The first stage receives a data signal representative of data and a clock signal, and may process the data at a first data rate equal to a clock rate of the clock signal. Each second stage may process respective data in response to a respective clock cycle received from the first stage at a second data rate equal to the first data rate times the number of second stages. The third stage may process data received from each second stage at the first data rate. The first stage divides the data signal and the clock signal between the plurality of second stages. The third stage merges the respective data and the respective clock cycles from each of the plurality of second stages to provide a merged data signal and a return clock signal.Type: ApplicationFiled: June 3, 2019Publication date: September 26, 2019Applicant: Micron Technology, Inc.Inventors: Kaveh Shakeri, Ali Feiz Zarrin Ghalam, Qiang Tang, Eric N. Lee
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Patent number: 10410698Abstract: A wave pipeline includes a plurality of data paths, a clock signal path, and a return clock signal path. Each data path includes an input node, an output node, and a data stage between the input node and the output node. Each data path has a different delay between the input node and the output node. A first data path of the plurality of data paths has a first delay and each of the other data paths of the plurality of data paths have a delay less than the first delay. The clock signal path provides a clock signal to the data stage of each data path. The return clock signal path provides a return clock signal from the data stage of the first data path. The return clock signal triggers data out of the data stage of each data path of the plurality of data paths.Type: GrantFiled: December 7, 2017Date of Patent: September 10, 2019Assignee: Micron Technology, Inc.Inventors: Kaveh Shakeri, Ali Feiz Zarrin Ghalam
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Publication number: 20190258400Abstract: Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock edge of a second clock signal; to generate a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal; and to latch data for output from the memory device in response to the second clock edge of the first clock signal.Type: ApplicationFiled: April 30, 2019Publication date: August 22, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Eric Lee, Qiang Tang, Ali Feiz Zarrin Ghalam, Hoon Choi, Daesik Song
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Patent number: 10387048Abstract: Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, to generate a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and to latch data for output from the memory device in response to the second clock edge of the first clock signal.Type: GrantFiled: June 12, 2018Date of Patent: August 20, 2019Assignee: Micron Technology, Inc.Inventors: Eric Lee, Qiang Tang, Ali Feiz Zarrin Ghalam, Hoon Choi, Daesik Song
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Patent number: 10360956Abstract: A wave pipeline includes a first stage, a plurality of second stages, and a third stage. The first stage receives a data signal representative of data and a clock signal, and may process the data at a first data rate equal to a clock rate of the clock signal. Each second stage may process respective data in response to a respective clock cycle received from the first stage at a second data rate equal to the first data rate times the number of second stages. The third stage may process data received from each second stage at the first data rate. The first stage divides the data signal and the clock signal between the plurality of second stages. The third stage merges the respective data and the respective clock cycles from each of the plurality of second stages to provide a merged data signal and a return clock signal.Type: GrantFiled: December 7, 2017Date of Patent: July 23, 2019Assignee: Micron Technology, Inc.Inventors: Kaveh Shakeri, Ali Feiz Zarrin Ghalam, Qiang Tang, Eric N. Lee
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Publication number: 20190190501Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.Type: ApplicationFiled: November 29, 2018Publication date: June 20, 2019Inventors: Guan Wang, Qiang Tang, Ali Feiz Zarrin Ghalam
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Publication number: 20190180801Abstract: A wave pipeline includes a first stage, a plurality of second stages, and a third stage. The first stage receives a data signal representative of data and a clock signal, and may process the data at a first data rate equal to a clock rate of the clock signal. Each second stage may process respective data in response to a respective clock cycle received from the first stage at a second data rate equal to the first data rate times the number of second stages. The third stage may process data received from each second stage at the first data rate. The first stage divides the data signal and the clock signal between the plurality of second stages. The third stage merges the respective data and the respective clock cycles from each of the plurality of second stages to provide a merged data signal and a return clock signal.Type: ApplicationFiled: December 7, 2017Publication date: June 13, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Kaveh Shakeri, Ali Feiz Zarrin Ghalam, Qiang Tang, Eric N. Lee
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Publication number: 20190180802Abstract: A wave pipeline includes a plurality of data paths, a clock signal path, and a return clock signal path. Each data path includes an input node, an output node, and a data stage between the input node and the output node. Each data path has a different delay between the input node and the output node. A first data path of the plurality of data paths has a first delay and each of the other data paths of the plurality of data paths have a delay less than the first delay. The clock signal path provides a clock signal to the data stage of each data path. The return clock signal path provides a return clock signal from the data stage of the first data path. The return clock signal triggers data out of the data stage of each data path of the plurality of data paths.Type: ApplicationFiled: December 7, 2017Publication date: June 13, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Kaveh Shakeri, Ali Feiz Zarrin Ghalam
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Patent number: 10270429Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.Type: GrantFiled: December 20, 2017Date of Patent: April 23, 2019Assignee: Micron Technology, Inc.Inventors: Guan Wang, Qiang Tang, Ali Feiz Zarrin Ghalam
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Publication number: 20180292990Abstract: Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, to generate a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and to latch data for output from the memory device in response to the second clock edge of the first clock signal.Type: ApplicationFiled: June 12, 2018Publication date: October 11, 2018Applicant: MICRON TECHNOLOGY, INC.Inventors: Eric Lee, Qiang Tang, Ali Feiz Zarrin Ghalam, Hoon Choi, Daesik Song
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Patent number: 10019170Abstract: In an example, a method of operating a memory device to latch data for output from the memory device may include generating a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, generating a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and latching the data in response to the second clock edge of the first clock signal for output from the memory device.Type: GrantFiled: March 30, 2016Date of Patent: July 10, 2018Assignee: Micron Technology, Inc.Inventors: Eric Lee, Qiang Tang, Ali Feiz Zarrin Ghalam, Hoon Choi, Daesik Song
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Publication number: 20170285938Abstract: In an example, a method of operating a memory device to latch data for output from the memory device may include generating a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, generating a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and latching the data in response to the second clock edge of the first clock signal for output from the memory device.Type: ApplicationFiled: March 30, 2016Publication date: October 5, 2017Applicant: MICRON TECHNOLOGY, INC.Inventors: Eric Lee, Qiang Tang, Ali Feiz Zarrin Ghalam, Hoon Choi, Daesik Song
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Patent number: 9710182Abstract: Apparatuses and methods for reducing capacitance on a data bus are disclosed herein. In accordance with one or more described embodiments, an apparatus may comprise a plurality of memories coupled to an internal data bus and a command and address bus, each of the memories configured to receive a command on the command and address bus. One of the plurality of memories may be coupled to an external data bus. The one of the plurality of memories may be configured to provide program data to the internal data bus when the command comprises a program command and another of the plurality of memories is a target memory of the program command and may be configured to provide read data to the external data bus when the command comprises a read command and the another of the plurality of memories is a target memory of the read command.Type: GrantFiled: November 16, 2015Date of Patent: July 18, 2017Assignee: Micron Technology, Inc.Inventors: Dean K. Nobunaga, Ali Feiz Zarrin Ghalam, Xiaojiang Guo, Eric N. Lee
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Patent number: 9460803Abstract: A system includes a plurality of sensing devices, a first multiplexer, a plurality of local return clock signal paths, a second multiplexer, and a data latch. Each sensing device outputs data onto a respective local data path in response to a clock signal on a clock signal path. The first multiplexor passes data from a selected local data path to a global data path. Each local return clock signal path is coupled to the clock signal path at a respective sensing device such that each local return clock signal path is routed along with a respective local data path. The second multiplexor passes a return clock signal from a selected local return clock signal path corresponding to the selected local data path to a global return clock signal path. The data latch latches the data on the global data path into the data latch in response to the return clock signal on the global return clock signal path.Type: GrantFiled: September 25, 2015Date of Patent: October 4, 2016Assignee: Micron Technology, Inc.Inventors: Qiang Tang, Ali Feiz Zarrin Ghalam, Hoon Choi, Eric N. Lee, Ramin Ghodsi
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Patent number: 9401188Abstract: Examples of devices and systems including enabling circuits are described. Two voltage supplies may be used to operate different portions of the devices, including peripheral circuits and I/O circuits. When the voltage supply to the peripheral circuits of one or more devices is disabled, the I/O circuits of that device may be disabled. In some examples, power may advantageously be saved in part by eliminating or reducing a DC current path through the I/O circuits.Type: GrantFiled: March 17, 2014Date of Patent: July 26, 2016Assignee: Micron Technology, Inc.Inventors: Toru Tanzawa, Ali Feiz Zarrin Ghalam
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Publication number: 20160070504Abstract: Apparatuses and methods for reducing capacitance on a data bus are disclosed herein. In accordance with one or more described embodiments, an apparatus may comprise a plurality of memories coupled to an internal data bus and a command and address bus, each of the memories configured to receive a command on the command and address bus. One of the plurality of memories may be coupled to an external data bus, The one of the plurality of memories may be configured to provide program data to the internal data bus when the command comprises a program command and another of the plurality of memories is a target memory of the program command and may be configured to provide read data to the external data bus when the command comprises a read command and the another of the plurality of memories is a target memory of the read command.Type: ApplicationFiled: November 16, 2015Publication date: March 10, 2016Inventors: Dean K. Nobunaga, Ali Feiz Zarrin Ghalam, Xiaojiang Guo, Eric N. Lee
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Patent number: 9190133Abstract: Apparatuses and methods for reducing capacitance on a data bus are disclosed herein. In accordance with one or more described embodiments, an apparatus may comprise a plurality of memories coupled to an internal data bus and a command and address bus, each of the memories configured to receive a command on the command and address bus. One of the plurality of memories may be coupled to an external data bus. The one of the plurality of memories may be configured to provide program data to the internal data bus when the command comprises a program command and another of the plurality of memories is a target memory of the program command and may be configured to provide read data to the external data bus when the command comprises a read command and the another of the plurality of memories is a target memory of the read command.Type: GrantFiled: March 11, 2013Date of Patent: November 17, 2015Assignee: Micron Technology, Inc.Inventors: Dean K. Nobunaga, Ali Feiz Zarrin Ghalam, Xiaojiang Guo, Eric N. Lee
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Publication number: 20140258619Abstract: Apparatuses and methods for reducing capacitance on a data bus are disclosed herein. In accordance with one or more described embodiments, an apparatus may comprise a plurality of memories coupled to an internal data bus and a command and address bus, each of the memories configured to receive a command on the command and address bus. One of the plurality of memories may be coupled to an external data bus. The one of the plurality of memories may be configured to provide program data to the internal data bus when the command comprises a program command and another of the plurality of memories is a target memory of the program command and may be configured to provide read data to the external data bus when the command comprises a read command and the another of the plurality of memories is a target memory of the read command.Type: ApplicationFiled: March 11, 2013Publication date: September 11, 2014Applicant: Micron Technology, Inc.Inventors: Dean K. Nobunaga, Ali Feiz Zarrin Ghalam, Xiaojiang Guo, Eric N. Lee
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Publication number: 20140198586Abstract: Examples of devices and systems including enabling circuits are described. Two voltage supplies may be used to operate different portions of the devices, including peripheral circuits and I/O circuits. When the voltage supply to the peripheral circuits of one or more devices is disabled, the I/O circuits of that device may be disabled. In some examples, power may advantageously be saved in part by eliminating or reducing a DC current path through the I/O circuits.Type: ApplicationFiled: March 17, 2014Publication date: July 17, 2014Applicant: Micron Technology, Inc.Inventors: Toru Tanzawa, Ali Feiz Zarrin Ghalam
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Patent number: 8675420Abstract: Examples of devices and systems including enabling circuits are described. Two voltage supplies may be used to operate different portions of the devices, including peripheral circuits and I/O circuits. When the voltage supply to the peripheral circuits of one or more devices is disabled, the I/O circuits of that device may be disabled. In some examples, power may advantageously be saved in part by eliminating or reducing a DC current path through the I/O circuits.Type: GrantFiled: May 26, 2011Date of Patent: March 18, 2014Assignee: Micron Technology, Inc.Inventors: Toru Tanzawa, Ali Feiz Zarrin Ghalam