Patents by Inventor Ali Mohammadzadeh
Ali Mohammadzadeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180349029Abstract: The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.Type: ApplicationFiled: May 31, 2017Publication date: December 6, 2018Inventors: Ali Mohammadzadeh, Jung Sheng Hoei, Dheeraj Srinivasan, Terry M. Grunzke
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Patent number: 10120604Abstract: Apparatuses and methods for performing buffer operations in memory are provided. An example apparatus can include an array of memory cells, a page buffer, and a controller. The page buffer can be configured to store a number of pages of data in respective caches of the page buffer. The controller can be configured to program the number of pages of data to a first group of cells in the array. The programming operation can include programming the first group of cells to target states encoded with respective data patterns. The programming operation can include incrementally releasing a first of the respective caches of the page buffer responsive to completing programming of cells programmed to a particular first one of the target states, and a second of the respective caches of the page buffer responsive to completing programming of cells programmed to a particular second one of the target states.Type: GrantFiled: June 13, 2017Date of Patent: November 6, 2018Assignee: Micron Technology, Inc.Inventors: Dheeraj Srinivasan, Ali Mohammadzadeh
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Publication number: 20180301193Abstract: The present disclosure relates to apparatuses and methods for an automated dynamic word line start voltage (ADWLSV). An example apparatus includes a controller and a memory device. The memory device is configured to maintain, internal to the memory device, a status of a number of open blocks in the memory device. The status can include a programming operation being initiated in the respective number of open blocks. Responsive to receipt of, from the controller, a request to direct initiation of the programming operation to a word line, determine a group of memory cells associated with the word line that programs first relative to other groups of memory cells associated with the word line and maintain, included in the status of an open block, a voltage at which the group of memory cells is the first group to program.Type: ApplicationFiled: March 21, 2017Publication date: October 18, 2018Inventors: Dheeraj Srinivasan, Jeffrey M. Tsai, Ali Mohammadzadeh, Terry M. Grunzke
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Publication number: 20180210653Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.Type: ApplicationFiled: January 23, 2017Publication date: July 26, 2018Inventors: Sivagnanam Parthasarathy, Terry M. Grunzke, Lucia Botticchio, Walter Di Francesco, Vamshi K. Indavarapu, Gianfranco Valeri, Renato C. Padilla, Ali Mohammadzadeh, Jung Sheng Hoei, Luca De Santis
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Publication number: 20180137921Abstract: Memory devices including an array of memory cells, a plurality of access lines selectively coupled to respective pluralities of memory cells of the array of memory cells, a plurality of first registers, a second register, a first multiplexer, a second multiplexer, and a decoder configured to selectively connect a corresponding access line to a selected voltage source of a plurality of voltage sources in response to the output of the second multiplexer, wherein the second multiplexer is configured to pass a selected one of the output of the second register and the output of the first multiplexer to its output, and wherein the first multiplexer is configured to pass a selected one of the outputs of the plurality of first registers to its output.Type: ApplicationFiled: January 12, 2018Publication date: May 17, 2018Applicant: MICRON TECHNOLOGY, INC.Inventors: Benjamin Louie, Ali Mohammadzadeh, Aaron S. Yip
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Patent number: 9881675Abstract: Technology for performing addressing in a NAND memory is described. A defined number of address cycles supported at either a memory controller or a NAND memory to address individual memory units in the NAND memory can be identified. The defined number of address cycles in which to operate can be selected in order to address the individual memory units in the NAND memory. Either the memory controller or the NAND memory can be configured to operate at the selected number of address cycles where the individual memory units in the NAND memory are uniquely addressable using a multi die select (MDS).Type: GrantFiled: November 21, 2016Date of Patent: January 30, 2018Assignee: Intel CorporationInventors: Umberto Siciliani, Tommaso Vali, Terry Grunzke, Ali Mohammadzadeh
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Patent number: 9875802Abstract: Memory devices are configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.Type: GrantFiled: November 3, 2016Date of Patent: January 23, 2018Assignee: Micron Technology, Inc.Inventors: Benjamin Louie, Ali Mohammadzadeh, Aaron S. Yip
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Publication number: 20170076806Abstract: Memory devices are configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.Type: ApplicationFiled: November 3, 2016Publication date: March 16, 2017Applicant: MICRON TECHNOLOGY, INC.Inventors: Benjamin Louie, Ali Mohammadzadeh, Aaron S. Yip
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Publication number: 20170069385Abstract: Technology for performing addressing in a NAND memory is described. A defined number of address cycles supported at either a memory controller or a NAND memory to address individual memory units in the NAND memory can be identified. The defined number of address cycles in which to operate can be selected in order to address the individual memory units in the NAND memory. Either the memory controller or the NAND memory can be configured to operate at the selected number of address cycles where the individual memory units in the NAND memory are uniquely addressable using a multi die select (MDS).Type: ApplicationFiled: November 21, 2016Publication date: March 9, 2017Applicant: Intel CorporationInventors: Umberto Siciliani, Tommaso Vali, Terry Grunzke, Ali Mohammadzadeh
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Patent number: 9514829Abstract: Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.Type: GrantFiled: December 3, 2015Date of Patent: December 6, 2016Assignee: Micron Technology, Inc.Inventors: Benjamin Louie, Ali Mohammadzadeh, Aaron S. Yip
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Patent number: 9502118Abstract: Technology for performing addressing in a NAND memory is described. A defined number of address cycles supported at either a memory controller or a NAND memory to address individual memory units in the NAND memory can be identified. The defined number of address cycles in which to operate can be selected in order to address the individual memory units in the NAND memory. Either the memory controller or the NAND memory can be configured to operate at the selected number of address cycles where the individual memory units in the NAND memory are uniquely addressable using a multi die select (MDS).Type: GrantFiled: September 26, 2014Date of Patent: November 22, 2016Assignee: Intel CorporationInventors: Umberto Siciliani, Tommaso Vali, Terry Grunzke, Ali Mohammadzadeh
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Publication number: 20160093379Abstract: Technology for performing addressing in a NAND memory is described. A defined number of address cycles supported at either a memory controller or a NAND memory to address individual memory units in the NAND memory can be identified. The defined number of address cycles in which to operate can be selected in order to address the individual memory units in the NAND memory. Either the memory controller or the NAND memory can be configured to operate at the selected number of address cycles where the individual memory units in the NAND memory are uniquely addressable using a multi die select (MDS).Type: ApplicationFiled: September 26, 2014Publication date: March 31, 2016Inventors: Umberto Siciliani, Tommaso Vali, Terry Grunzke, Ali Mohammadzadeh
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Publication number: 20160086672Abstract: Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.Type: ApplicationFiled: December 3, 2015Publication date: March 24, 2016Applicant: MICRON TECHNOLOGY, INC.Inventors: Benjamin Louie, Ali Mohammadzadeh, Aaron S. Yip
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Patent number: 9218884Abstract: Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.Type: GrantFiled: January 13, 2014Date of Patent: December 22, 2015Assignee: Micron Technology, Inc.Inventors: Benjamin Louie, Ali Mohammadzadeh, Aaron S. Yip
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Publication number: 20140126297Abstract: Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.Type: ApplicationFiled: January 13, 2014Publication date: May 8, 2014Applicant: Micron Technology, Inc.Inventors: Benjamin Louie, Ali Mohammadzadeh, Aaron S. Yip
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Patent number: 8638632Abstract: Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.Type: GrantFiled: September 23, 2010Date of Patent: January 28, 2014Assignee: Micron Technology, Inc.Inventors: Benjamin Louie, Ali Mohammadzadeh, Aaron Yip
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Publication number: 20120075934Abstract: Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.Type: ApplicationFiled: September 23, 2010Publication date: March 29, 2012Inventors: Benjamin Louie, Ali Mohammadzadeh, Aaron Yip