Abstract: An electronic display may include a first anode configured to carry a red emission signal, a second anode configured to carry a blue emission signal, a third anode configured to carry a green emission signal, and a micro-driver configured to stagger a timing of the red emission signal, the blue emission signal, and the green emission signal based on an emission clock signal to display image content on the electronic display.

Abstract: An apparatus and method for enhanced downlink processing of received channels in a mobile communications system is described, containing a buffer for control data and traffic data, a demapper engine with at least two independently operating demappers for demapping the control and traffic data, a log-likelihood-ratio (LLR) buffer for supporting memory segments accessible by the demapper engine, a decoder engine containing decoders, each of the decoders operating on data from selected memory segment(s) of the LLR buffer, and an arbitrator providing control of at least one of the demapper engine, LLR buffer, and decoder engine. At least one of the decoders is suited for decoding control data and another one of the decoders is suited for decoding traffic data. By partitioning the decoding as such, an increase in downlink throughput can be obtained.

Abstract: A de-interleaver generates a plurality of De-interleaved Reorder Physical (DRP) addresses to simultaneously write a corresponding plurality of LLR values into a multi-banked memory such that not more than one LLR value is written into each bank of the multi-banked memory at a time. A sequence of such parallel writes results in the LLR values of a transmission of a sub-packet being stored in the memory. Address translation performed during generation of the DRP addresses causes the LLR values to be stored within the banks such that a decoder can read LLR values out of the memory in a de-interleaved sequence. Each memory location of a bank is a word-location for storing multiple related LLR values, where one LLR value is stored along with its parity values. The ability to simultaneously write to multiple LLR values is used to clear locations in a fast and efficient manner.

Abstract: A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.

Abstract: An apparatus and method for enhanced downlink processing of received channels in a mobile communications system is described, containing a buffer for control data and traffic data, a demapper engine with at least two independently operating demappers for demapping the control and traffic data, a log-likelihood-ratio (LLR) buffer for supporting memory segments accessible by the demapper engine, a decoder engine containing decoders, each of the decoders operating on data from selected memory segment(s) of the LLR buffer, and an arbitrator providing control of at least one of the demapper engine, LLR buffer, and decoder engine. At least one of the decoders is suited for decoding control data and another one of the decoders is suited for decoding traffic data. By partitioning the decoding as such, an increase in downlink throughput can be obtained.

Abstract: A de-interleaver involves logic that receives a seed and that simultaneously generates from the seed a plurality of reorder indices. The plurality of reorder indices is usable for de-interleaving an incoming stream of interleaved code bits. Each plurality of simultaneously generated reorder indices generated corresponds to a set of simultaneously received code bits in the incoming stream. The reorder indices are converted into physical addresses in parallel and these physical addresses are used to store the set of code bits into a memory. Code bits for multiple sub-packets of different sub-packet sizes are typically present in memory at the same time. The code bits are then read out of memory to form an outgoing stream of de-interleaved code bits. The de-interleaver has a pipelined architecture such that sets of code bits are written into the memory at the same rate that sets of code bits are received onto the de-interleaver.

Abstract: A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.

Abstract: A de-interleaver generates a plurality of De-interleaved Reorder Physical (DRP) addresses to simultaneously write a corresponding plurality of LLR values into a multi-banked memory such that not more than one LLR value is written into each bank of the multi-banked memory at a time. A sequence of such parallel writes results in the LLR values of a transmission of a sub-packet being stored in the memory. Address translation performed during generation of the DRP addresses causes the LLR values to be stored within the banks such that a decoder can read LLR values out of the memory in a de-interleaved sequence. Each memory location of a bank is a word-location for storing multiple related LLR values, where one LLR value is stored along with its parity values. The ability to simultaneously write to multiple LLR values is used to clear locations in a fast and efficient manner.