Patents by Inventor Ali S. El-Zein
Ali S. El-Zein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240152676Abstract: A process is described to allow an early power estimate where switching activity provided by a simulation of a logical hierarchy in a chip design is accomplished by mapping ports in the physical hierarchy to ports in a logical hierarchy after hierarchy manipulation has been done. Power estimation is done using the switching activity from the simulation of the logical hierarchy mapped to the ports of the physical hierarchy. Early power estimation using results of the hierarchy manipulation is better than power estimation on the logical hierarchy because blocks and signals in the logical hierarchy may be replicated or merged during the hierarchy manipulation.Type: ApplicationFiled: November 9, 2022Publication date: May 9, 2024Inventors: Ali S. El-Zein, Robert James Shadowen, Gabor Bobok, Edward Armayor McQuade
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Patent number: 11663381Abstract: A processor receives, as input, a first hardware description language (HDL) file defining an entity of a modular circuit design. The first HDL file instantiates, by a storage element declaration in a hardware description language, a storage element within the entity. The first HDL file omits a port map for the storage element. Based on the first HDL file, the processor automatically fully elaborates a port map for the storage element. The processor stores, in data storage, a derived second HDL file defining the entity and including the port map.Type: GrantFiled: September 7, 2021Date of Patent: May 30, 2023Assignee: International Business Machines CorporationInventors: Stephen Gerard Shuma, Ali S. El-Zein, Wolfgang Roesner, Viresh Paruthi, Benedikt Geukes, Klaus-Dieter Schubert, Birgit Schubert, Stephen John Barnfield, Derek E. Williams
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Publication number: 20230075770Abstract: A processor receives, as input, a first hardware description language (HDL) file defining an entity of a modular circuit design. The first HDL file instantiates, by a storage element declaration in a hardware description language, a storage element within the entity. The first HDL file omits a port map for the storage element. Based on the first HDL file, the processor automatically fully elaborates a port map for the storage element. The processor stores, in data storage, a derived second HDL file defining the entity and including the port map.Type: ApplicationFiled: September 7, 2021Publication date: March 9, 2023Inventors: Stephen Gerard Shuma, Ali S. El-Zein, Wolfgang Roesner, Viresh Paruthi, Benedikt Geukes, Klaus-Dieter Schubert, Birgit Schubert, Stephen John Barnfield, Derek E. Williams
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Publication number: 20230074528Abstract: A first plurality of hardware description language (HDL) files defines a first scope of design forming only a subset of a larger hierarchical integrated circuit design. Technology-specific structures specific to a physical implementation are incorporated in the first scope of design. A second plurality of HDL files defining a first design entity that is at the first scope of design and that includes the technology-specific structures is generated. A third plurality of HDL files defining a second scope of design for the hierarchical integrated circuit design that is larger than and includes the first scope of design is formed. The third plurality of HDL files is processed to form a representation of the second scope of design. Processing the third plurality of HDL files includes replacing a second design entity in the second scope of design lacking at least some technology-specific structures with the first design entity.Type: ApplicationFiled: September 7, 2021Publication date: March 9, 2023Inventors: Ali S. El-Zein, Wolfgang Roesner, Viresh Paruthi, Stephen Gerard Shuma, Stephen John Barnfield, Maya Safieddine, Benedikt Geukes, Klaus-Dieter Schubert, Gabor Drasny
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Publication number: 20230070516Abstract: A first plurality of hardware description language (HDL) files describe a hierarchical integrated circuit design utilizing a simplified HDL syntax that omits specification of logical clock connections for at least some entities in the hierarchical integrated circuit design. The hierarchical integrated circuit design as described by the first plurality of HDL files is processed to automatically add logical clock connections for entities in the hierarchical integrated circuit design for which specification of logical clock connections are omitted in the first plurality of HDL files. Based on the processing, a second plurality of HDL files defining the hierarchical integrated circuit design is generated.Type: ApplicationFiled: September 7, 2021Publication date: March 9, 2023Inventors: Ali S. El-Zein, Viresh Paruthi, Alvan Wing Ng, Benedikt Geukes, Klaus-Dieter Schubert, Robert Alan Cargnoni, Michael Hemsley Wood, Stephen Gerard Shuma, Wolfgang Roesner, Chung-Lung K. Shum, Edward Armayor McQuade, Derek E. Williams
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Publication number: 20230075565Abstract: Based on a directive in a control file, a processor pre-routes, within a hierarchical integrated circuit design, a signal through one or more levels of design hierarchy between a signal source at a higher level of the design hierarchy and an entity instance at a lower level of the design hierarchy. The processor processes entity instances in the design hierarchy in a bottom-up manner to insert technology-specific structures into the hierarchical integrated circuit design. During the processing, the processor inserts into a particular entity instance of the design hierarchy a technology-specific structure and connects the technology-specific structure to the signal pre-routed to the particular entity instance by the pre-routing.Type: ApplicationFiled: September 7, 2021Publication date: March 9, 2023Inventors: Wolfgang Roesner, Ali S. El-Zein, Viresh Paruthi, Stephen Gerard Shuma, Stephen John Barnfield, Alvan Wing Ng, Robert James Shadowen
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Publication number: 20230072735Abstract: A processor receives an expression of design refinement intent with regard to an entity forming a part of a modular circuit design. The entity is defined by a hardware description language (HDL) file, and the expression of design refinement intent identifies an intent region within an implementation of the entity and specifies replacement logic for the region. Based on the expression of design refinement intent, the processor automatically modifies the HDL file by replacing logic within the intent region with the replacement logic. The processor then performs logical synthesis to generate a gate list representation of the modular circuit design as modified.Type: ApplicationFiled: September 7, 2021Publication date: March 9, 2023Inventors: Ali S. El-Zein, Wolfgang Roesner, Stephen Gerard Shuma, Robert Lowell Kanzelman, Michael Hemsley Wood, Chung-Lung K. Shum, Gabor Bobok, Robert James Shadowen, Viresh Paruthi, Derek E. Williams
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Patent number: 10599804Abstract: Method and apparatus for managing connections within a netlist include using a clone module to the connections between different components within the netlist. A buffer may be inserted between components of a netlist to split a connection into multiple segments and then moved into an associated first instance. The inclusion of the buffer allows for one or more of pin cloning and subway utilization to occur when mapping between a functional hierarchy to a physical hierarchy is performed.Type: GrantFiled: November 1, 2018Date of Patent: March 24, 2020Assignee: International Business Machines CorporationInventors: Ali S. El-Zein, Robert J. Shadowen, Alvan W. Ng, Clay C. Smith, Wolfgang Roesner
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Patent number: 10565338Abstract: Embodiments of the present invention provides methods, computer program products, and a system for processing hierarchical references for a formal equivalence check. In certain embodiments, hierarchical references of a first design are identified as functionally equivalent to hierarchical references of a second design. Value outputs of the first design can be compared to the value outputs of the second design to determine whether the value outputs of the respective designs match.Type: GrantFiled: December 13, 2017Date of Patent: February 18, 2020Assignee: International Business Machines CorporationInventors: Ali S. El-Zein, Mark A. Williams, Robert L. Kanzelman, Viresh Paruthi, Wolfgang Roesner
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Publication number: 20190179974Abstract: Embodiments of the present invention provides methods, computer program products, and a system for processing hierarchical references for a formal equivalence check. In certain embodiments, hierarchical references of a first design are identified as functionally equivalent to hierarchical references of a second design. Value outputs of the first design can be compared to the value outputs of the second design to determine whether the value outputs of the respective designs match.Type: ApplicationFiled: December 13, 2017Publication date: June 13, 2019Inventors: Ali S. El-Zein, Mark A. Williams, Robert L. Kanzelman, Viresh Paruthi, Wolfgang Roesner
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Patent number: 9495496Abstract: A method of non-invasive insertion of logic functions into a register-transfer level (RTL) design, including: selecting a logic function to insert into a RTL design; identifying each hierarchical level executing at least a portion of the logic function; identifying a highest hierarchical level amongst hierarchical levels having each hierarchical level executing at least a portion of the logic function; and inserting all connections necessary to execute the logic function into a hardware description representation of the highest hierarchical level, without modifying a hardware description representation of any other hierarchical levels.Type: GrantFiled: December 18, 2014Date of Patent: November 15, 2016Assignee: International Business Machines CorporationInventors: Stephen J. Barnfield, Ali S. El-Zein
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Publication number: 20160180000Abstract: Non-invasive insertion of logic functions into a RTL design, including: selecting a logic function to insert into an RTL design; identifying each hierarchical level executing at least a portion of the logic function; identifying a highest hierarchical level amongst each hierarchical level executing at least a portion of the logic function; and inserting all connections necessary to execute the logic function into a hardware description representation of the highest hierarchical level, without modifying a hardware description representation of any other hierarchical levels.Type: ApplicationFiled: December 18, 2014Publication date: June 23, 2016Inventors: STEPHEN J. BARNFIELD, ALI S. EL-ZEIN
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Patent number: 8443314Abstract: A logic design and synthesis program, method and system provides intelligibility and independence of separate blocks in digital logic designs at the synthesis level. The sequential and combinational logic are separated and the sequential logic is then mapped to flip-flop library components. State-retaining elements, i.e., flip-flops detected in the input hardware description language (HDL) are represented in the sequential logic HDL output. The combinational logic HDL and the sequential logic HDL are connected only by signals, so signals are introduced to represent the flip-flop signals and variables detected in the input HDL. The sequential and combinational logic HDL are then synthesized to produce the design.Type: GrantFiled: February 23, 2012Date of Patent: May 14, 2013Assignee: International Business Machines CorporationInventors: Ali S. El-Zein, Wolfgang Roesner, Robert J. Shadowen
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Patent number: 8234604Abstract: Co-Optimization utilizing Symbolic Execution (COSE) works across components of an embedded design to optimize structures therein. COSE utilizes symbolic execution (SE) to analyze software components and defines a limited set of values that software feeds hardware as constraints. SE explores substantially all possible paths of execution of the code specifying a component. It accomplishes this by accumulating path conditions (PCs) and annotating them to the corresponding segments of the component. A PC is associated with a branch of code and consists of the conjunction of conditions over input and state variables necessary and sufficient for the branch to execute. These PCs define constraints that limit the set of values that software feeds hardware. These constraints are then propagated across the networks of the design and employ static analysis techniques such as constant propagation, redundancy removal, and don't care optimizations to reduce the hardware components.Type: GrantFiled: September 2, 2008Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Ali S El-Zein, Fadi A Zaraket
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Patent number: 8140313Abstract: A method, system and computer program product for modeling variables in subprograms of a HDL program. A subprogram is provided with an initial value of a variable of an element being modeled and the subprogram is stored in memory of a data processing system. In response to a subprogram call, a copy of the stored subprogram is provided to the requesting HDL program. During execution, the initial value of the variable in the provided copy of the subprogram may be modified by the HDL program, but the value retains unchanged in the stored subprogram.Type: GrantFiled: January 30, 2008Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Gabor Drasny, Ali S. El-Zein, Wolfgang Roesner, Fadi A. Zaraket
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Patent number: 8141048Abstract: A method of verifying a software system includes receiving a description of a software system described utilizing a high-level modeling language, and responsive thereto, parsing the description and constructing an abstract syntax graph. The abstract syntax graph is transformed into a sequential logic representation of the software system. The sequential logic representation is formed by reference to a Hardware Description Language (HDL) library. Then, the sequential logic representation is transformed into a gate-level sequential logic representation. Following the transforming, the software system is verified based upon the gate-level sequential logic representation. Following verification, results of verification of the software system are output.Type: GrantFiled: February 22, 2007Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Jason R. Baumgartner, Ali S. El-Zein, Viresh Paruthi, Fadi A. Zaraket
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Publication number: 20100058256Abstract: Co-Optimization utilizing Symbolic Execution (COSE) works across components of an embedded design to optimize structures therein. COSE utilizes symbolic execution (SE) to analyze software components and defines a limited set of values that software feeds hardware as constraints. SE explores substantially all possible paths of execution of the code specifying a component. It accomplishes this by accumulating path conditions (PCs) and annotating them to the corresponding segments of the component. A PC is associated with a branch of code and consists of the conjunction of conditions over input and state variables necessary and sufficient for the branch to execute. These PCs define constraints that limit the set of values that software feeds hardware. These constraints are then propagated across the networks of the design and employ static analysis techniques such as constant propagation, redundancy removal, and don't care optimizations to reduce the hardware components.Type: ApplicationFiled: September 2, 2008Publication date: March 4, 2010Applicant: International Business Machines CorporationInventors: ALI S. EL-ZEIN, Fadi A. Zaraket
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Publication number: 20090193390Abstract: A method, system and computer program product for modeling variables in subprograms of a HDL program. A subprogram is provided with an initial value of a variable of an element being modeled and the subprogram is stored in memory of a data processing system. In response to a subprogram call, a copy of the stored subprogram is provided to the requesting HDL program. During execution, the initial value of the variable in the provided copy of the subprogram may be modified by the HDL program, but the value retains unchanged in the stored subprogram.Type: ApplicationFiled: January 30, 2008Publication date: July 30, 2009Inventors: GABOR DRASNY, Alis S. El-Zein, Wolfgang Roesner, Fadi A. Zaraket
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Publication number: 20080209389Abstract: A method of verifying a software system includes receiving a description of a software system described utilizing a high-level modeling language, and responsive thereto, parsing the description and constructing an abstract syntax graph. The abstract syntax graph is transformed into a sequential logic representation of the software system, and following the transforming, the software system is verified based upon the sequential logic representation. Following verification, results of verification of the software system are output.Type: ApplicationFiled: February 22, 2007Publication date: August 28, 2008Inventors: Jason R. Baumgartner, Ali S. El-Zein, Viresh Paruthi, Fadi A. Zaraket
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Patent number: 7284210Abstract: A method, system and computer program product for performing testing and verification is disclosed. The method includes converting a bias data specification to a driver specification. The driver specification is then parsed into a base constraint and bias file, wherein the base constraint and bias file is suitable for conversion into one of a set comprising a netlist representation and a random simulation representation. A verification framework is selected from among a set comprising a random verification framework using the random simulation representation and a synthesized verification framework using the netlist representation. In response to selecting the random verification framework using the random simulation representation, the random simulation representation is compiled into a parameter database. In response to selecting the synthesized verification framework using the netlist representation, the netlist representation is compiled into a synthesized model.Type: GrantFiled: February 3, 2005Date of Patent: October 16, 2007Assignee: International Business Machines CorporationInventors: Jason Raymond Baumgartner, Ali S. El-Zein, Daniel Scott Heller, Wolfgang Roesner