Abstract: A mixer for a transmitter includes a voltage converter to convert a baseband voltage to a baseband current. A mixer component mixes the baseband current with a local oscillator frequency. An output of the mixer component includes a radio frequency signal and a higher order radio frequency signal. A coupler sends the radio frequency signal and the higher order radio frequency signal to a differential output. A filter is integrated into the coupler to filter the higher order radio frequency signal before being output by the differential output.

Abstract: A packaged integrated circuit includes an integrated circuit having a Radio Frequency (RF) passive element formed therein and a wafer level chip scale flip chip package that contains the integrated circuit. The wafer level chip scale flip chip package includes at least one dielectric layer isolating a top metal layer of the integrated circuit and a package signal connection upon the at least one dielectric layer, wherein the package signal connection partially overlays the RF passive element with respect to a surface of the integrated circuit. The RF passive element may be an inductor, a transformer, a capacitor, or another passive element. The package signal connection may be a conductive ball, a conductive bump, a conductive pad, or a conductive spring, for example. A conductive structure may reside upon the at least one dielectric layer to provide shielding to the RF passive element and may include a plurality of conductive elements or a mesh.

Abstract: A mixer for a transmitter includes a voltage converter to convert a baseband voltage to a baseband current. A mixer component mixes the baseband current with a local oscillator frequency. An output of the mixer component includes a radio frequency signal and a higher order radio frequency signal. A coupler sends the radio frequency signal and the higher order radio frequency signal to a differential output. A filter is integrated into the coupler to filter the higher order radio frequency signal before being output by the differential output.

Abstract: Disclosed herein is a method and circuit arrangement for a multi-layer ball grid array configuration. In one embodiment, there is presented a board comprising a first surface, a second surface, and a plurality of vias. The second surface is connected to the first surface. The plurality of vias are positioned to form a substantially straight line on the first surface. The plurality of vias comprises a first via and a second via. The first via is adjacent to the second via. The first via emerges on the second surface on one side of the substantially straight line. The second via emerges on another side of the substantially straight line.

Abstract: A packaged integrated circuit includes an integrated circuit having a Radio Frequency (RF) passive element formed therein and a wafer level chip scale flip chip package that contains the integrated circuit. The wafer level chip scale flip chip package includes at least one dielectric layer isolating a top metal layer of the integrated circuit and a package signal connection upon the at least one dielectric layer, wherein the package signal connection partially overlays the RF passive element with respect to a surface of the integrated circuit. The RF passive element may be an inductor, a transformer, a capacitor, a transistor, or another passive element. The package signal connection may be a conductive ball, a conductive bump, a conductive pad, or a conductive spring, for example. A conductive structure may reside upon the at least one dielectric layer to provide shielding to the RF passive element and may include a plurality of conductive elements or a mesh.

Abstract: Presented herein are ball grid array configurations for reducing path distances. In an exemplary embodiment, there is presented a memory system. The memory system comprises a printed circuit board, a memory controller, and a memory. The printed circuit board comprises a first layer and a second layer. The memory controller comprises a first plurality of pins connected to the first layer and a second plurality of pins connected to the second layer. The memory comprises a first plurality of pins connected to the first layer and a second plurality of pins connected to the second layer. The first layer comprises a plurality of connection paths connecting the first plurality of pins of the memory to the first plurality of pins of the memory controller. The second layer comprises a plurality of connection paths connecting the second plurality of pins of the memory to the second plurality of pins of the memory controller.

Abstract: An integrated circuit radio transceiver and method therefor includes an integrated circuit package that comprises a first substrate device, first and second nodes of a circuit on an outer surface of the first substrate device, a second substrate device and a trace on the second substrate device to provide crossover coupling. First and second bumps coupling the trace on the second substrate device to the first and second nodes on the first substrate device operable to provide crossover coupling.

Abstract: An integrated circuit radio transceiver and method therefor includes a balun formed to have interleaved traces which is operable to satisfy high current density requirements while reducing resistive and capacitive reactance of the balun to minimize coupling losses and to maintain efficiency. The interleaved traces may be selectively coupled according to design and application requirements.

Abstract: Disclosed herein is a method and circuit arrangement for a multi-layer ball grid array configuration. In one embodiment, there is presented a board comprising a first surface, a second surface, and a plurality of vias. The second surface is connected to the first surface. The plurality of vias are positioned to form a substantially straight line on the first surface. The plurality of vias comprises a first via and a second via. The first via is adjacent to the second via. The first via emerges on the second surface on one side of the substantially straight line. The second via emerges on another side of the substantially straight line.

Abstract: Presented herein are ball grid array configurations for reducing path distances. In an exemplary embodiment, there is presented a memory system. The memory system comprises a printed circuit board, a memory controller, and a memory. The printed circuit board comprises a first layer and a second layer. The memory controller comprises a first plurality of pins connected to the first layer and a second plurality of pins connected to the second layer. The memory comprises a first plurality of pins connected to the first layer and a second plurality of pins connected to the second layer. The first layer comprises a plurality of connection paths connecting the first plurality of pins of the memory to the first plurality of pins of the memory controller. The second layer comprises a plurality of connection paths connecting the second plurality of pins of the memory to the second plurality of pins of the memory controller.