Abstract: In an example, a method includes identifying, using at least one processor, data portions of a plurality of distinct data objects stored in at least one memory which are to be processed using the same logical operation. The method may further include identifying a representation of an operand stored in at least one memory, the operand being to provide the logical operation and providing a logical engine with the operand. The data portions may be stored in a plurality of input data buffers, wherein each of the input data buffers comprises a data portion of a different data object. The logical operation may be carried out on each of the data portions using the logical engine, and the outputs for each data portion may be stored in a plurality of output data buffers, wherein each of the outputs comprising data derived from a different data object.

Abstract: Examples disclosed herein include a dot product engine, which includes a resistive memory array to receive an input vector, perform a dot product operation on the input vector and a stored vector stored in the memory array, and output an analog signal representing a result of the dot product operation. The dot product engine includes a stored negation indicator to indicate whether elements of the stored vector have been negated, and a digital circuit to generate a digital dot product result value based on the analog signal and the stored negation indicator.

Abstract: Examples disclosed herein relate to a circuit having first and second analog processors and an analog-to-digital converter coupled to the first and second analog processors. The first analog processor provides a first analog signal having a voltage representing a function of a first vector and a second vector. The second analog processor provides a second analog signal having a voltage representing a function of a binary inverse of the first vector and the second vector. The analog-to-digital converter receives the first analog signal and the second analog signal, compares a signal selected from a group consisting of the first analog signal and the second analog signal to a reference voltage and based on the comparison to the reference voltage, determines a digital result representing the function of the first vector and the second vector.

Abstract: A circuit is provided. In an example, the circuit includes a memory array that includes a plurality of memory cells to store a matrix and a plurality of data lines coupled to the plurality of memory cells to provide a first set of values of the matrix. The circuit includes a multiplier coupled to the plurality of data lines to multiply the first set of values by a second set of values to produce a third set of values. A summing unit is included that is coupled to the multiplier to sum the third set of values to produce a sum. The circuit includes a shifting unit coupled to the summing unit to shift the sum and to add the shifted sum to a running total.

Abstract: Examples disclosed herein relate to a circuit having first and second analog processors and an analog-to-digital converter coupled to the first and second analog processors. The first analog processor provides a first analog signal having a voltage representing a function of a first vector and a second vector. The second analog processor provides a second analog signal having a voltage representing a function of a binary inverse of the first vector and the second vector. The analog-to-digital converter receives the first analog signal and the second analog signal, compares a signal selected from a group consisting of the first analog signal and the second analog signal to a reference voltage and based on the comparison to the reference voltage, determines a digital result representing the function of the first vector and the second vector.

Abstract: A circuit is provided. In an example, the circuit includes a memory array that includes a plurality of memory cells to store a matrix and a plurality of data lines coupled to the plurality of memory cells to provide a first set of values of the matrix. The circuit includes a multiplier coupled to the plurality of data lines to multiply the first set of values by a second set of values to produce a third set of values. A summing unit is included that is coupled to the multiplier to sum the third set of values to produce a sum. The circuit includes a shifting unit coupled to the summing unit to shift the sum and to add the shifted sum to a running total.

Abstract: In an example, a method includes receiving, in a memory, input data to be processed in a first and a second processing layer. A processing operation of the second layer may be carried out on an output of a processing operation of the first processing layer. The method may further include assigning the input data to be processed according to at least one processing operation of the first layer, which may comprise using a resistive memory array, and buffering output data. It may be determined whether the buffered output data exceeds a threshold data amount to carry out at least one processing operation of the second layer and when it is determined that the buffered output data exceeds the threshold data amount, at least a portion of the buffered output data may be assigned to be processed according to a processing operation of the second layer.

Abstract: Examples herein relate to circuits for computing vector-matrix multiplications involving negative values. A first memory crossbar array may be mapped to a first matrix which includes the positive values of an input matrix. A second memory crossbar array may be mapped to a second matrix which includes the negative values of the input matrix. An analog-to-digital converter may generate digital intermediate multiplication results based on analog results computed by the memory crossbar arrays. The digital intermediate multiplication results may include an intermediate result corresponding to a multiplication of each of the first vector and second vector with each of the first matrix and the second matrix. A controller may aggregate the digital intermediate results to generate a combined multiple result that represents the vector-matrix multiplication of the input vector and the input matrix.

Abstract: Examples herein relate to circuits for computing vector-matrix multiplications involving negative values. A first memory crossbar array may be mapped to a first matrix which includes the positive values of an input matrix. A second memory crossbar array may be mapped to a second matrix which includes the negative values of the input matrix. An analog-to-digital converter may generate digital intermediate multiplication results based on analog results computed by the memory crossbar arrays. The digital intermediate multiplication results may include an intermediate result corresponding to a multiplication of each of the first vector and second vector with each of the first matrix and the second matrix. A controller may aggregate the digital intermediate results to generate a combined multiple result that represents the vector-matrix multiplication of the input vector and the input matrix.

Abstract: This invention relates to a stereoselective preparation of fluoroleucine alkyl esters.

Abstract: This invention relates to a stereoselective preparation of fluoroleucine alkyl esters.

Abstract: Natural products such as certain chaetochromins are described. These compounds are useful in the inhibition of HIV integrase, the prevention or treatment of infection by HIV and the treatment of AIDS, either as compounds, pharmaceutically acceptable salts, pharmaceutical composition ingredients, whether or not in combination with other antivirals, immunomodulators, antibiotics or vaccines. Methods of treating AIDS and methods of preventing or treating infection by HIV are also described.

Abstract: There is disclosed a dual compartment solid phase extraction cartridge comprising a container divided into a top volume and a bottom volume by a porous filter or frit, the top and bottom volumes having a quantity of sorbent. The cartridge is useful in the separation of components of a liquid and solid mixture.

Abstract: Natural products such as certain chaetochromins are described. These compounds are useful in the inhibition of HIV integrase, the prevention or treatment of infection by HIV and the treatment of AIDS, either as compounds, pharmaceutically acceptable salts, pharmaceutical composition ingredients, whether or not in combination with other antivirals, immunomodulators, antibiotics or vaccines. Methods of treating AIDS and methods of preventing or treating infection by HIV are also described.

Abstract: Biotransformation products of a fermentation with Streptomyces sp., (Merck Culture Collection MA7165) ATCC No. 55946 are potent antifungal agents. These products may be useful in the treatment of diseases caused by fungal pathogens such as Candida sp. and Cryptococcus neoformans.

Abstract: Natural products such as certain ermophilane sesquiterpenoids and derivatives thereof are described. These compounds are useful in the inhibition of HIV integrase, the prevention or treatment of infection by HIV and the treatment of AIDS, either as compounds, pharmaceutically acceptable salts, pharmaceutical composition ingredients, whether or not in combination with other antivirals, immunomodulators, antibiotics or vaccines. Methods of treating AIDS and methods of preventing or treating infection by HIV are also described. The fungal culture MF6254, Xylaria sp. (ATCC 74397) is also described and disclosed.

Abstract: The present invention is directed to expression cassettes useful in gene expression studies in both homologous and heterologous Streptomyces strains. More specifically the present invention is directed to the construction of two Streptomyces lividans-recombinant strains capable of producing 31-O-desmethylFK-506 O:methyltransferase, which methvlates 31-O-desmethylFK-506 to FK-506. In addition, the present invention is directed to a process for the specific methylation of 31-desmethyl-FK506 to FK506.

Abstract: Biotransformation products of a fermentation with culture MA7074 are potent HIV protease inhibitors. These products are useful in the prevention or treatment of infection by HIV and in the treatment of AIDS, either as compounds, pharmaceutically acceptable salts, pharmaceutical composition ingredients, whether or not in combination with other antivirals, immunomodulators, antibiotics or vaccines. Methods of treating AIDS and methods of preventing or treating infection by HIV are also described.

Abstract: The present invention provides a process for the stereoselective reduction of phenylalkyl ketones to their corresponding (S)-hydroxy compounds. The process utilizes the novel microorganism Microbacterium MB 5614 to effectuate the chiral reduction. The present invention also provides said novel Microbacterium, which has been deposited with the ATCC and assigned the accession number ATCC 55557.

Abstract: A process for reducing a phenylalkyl ketone to the corresponding (S)-hydroxy derivative is disclosed. The process comprises contacting the phenylalkyl ketone with Mucor hiemalis IFO 5834 and recovering the (S)-hydroxy derivative.