Patents by Inventor Alina Vinslava

Alina Vinslava has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10461155
    Abstract: A semiconductor structure including a source/drain region is disclosed. The source/drain region may include a first epitaxial region along at least one sidewall of the source/drain region having a substantially uniform sidewall thickness. The semiconductor structure may further include a gate structure adjacent and above the source/drain region wherein at least a portion of the first epitaxial region is positioned below a sidewall spacer of the gate structure. A method of forming a source/drain region including a first epitaxial region having a substantially uniform sidewall thickness is disclosed. The method may include forming a trench in a substrate adjacent to a gate structure, forming the first epitaxial region in the trench, forming a spacer material layer on the gate structure and on a portion of the first epitaxial region, and removing a portion of the first epitaxial region using the spacer material layer as a mask.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: October 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yoong Hooi Yong, Yanping Shen, Hsien-Ching Lo, Xusheng Wu, Joo Tat Ong, Wei Hong, Yi Qi, Dongil Choi, Yongjun Shi, Alina Vinslava, James Psillas, Hui Zang
  • Patent number: 10355104
    Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region beneath a top surface of a semiconductor fin. The semiconductor fin is etched with an anisotropic etching process to form a cavity having a sidewall with a planar section extending vertically toward the top surface of the semiconductor fin and adjacent to the channel region in the semiconductor fin. The semiconductor fin is then etched with an isotropic etching process that widens the cavity at the top surface while preserving verticality of the planar section.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: July 16, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yi Qi, Sang Woo Lim, Kyung-Bum Koo, Alina Vinslava, Pei Zhao, Zhenyu Hu, Hsien-Ching Lo, Joseph F. Shepard, Jr., Shesh Mani Pandey
  • Publication number: 20190181243
    Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a first cavity extending into the semiconductor fin adjacent to the channel region. The semiconductor fin is etched with a second etching process to form a second cavity that is volumetrically smaller than the first cavity and that adjoins the first cavity.
    Type: Application
    Filed: February 14, 2019
    Publication date: June 13, 2019
    Inventors: Alina Vinslava, Hsien-Ching Lo, Yongjun Shi, Jianwei Peng, Jianghu Yan, Yi Qi
  • Patent number: 10297675
    Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a first cavity extending into the semiconductor fin adjacent to the channel region. The semiconductor fin is etched with a second etching process to form a second cavity that is volumetrically smaller than the first cavity and that adjoins the first cavity.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: May 21, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Alina Vinslava, Hsien-Ching Lo, Yongjun Shi, Jianwei Peng, Jianghu Yan, Yi Qi
  • Publication number: 20190148492
    Abstract: A semiconductor structure including a source/drain region is disclosed. The source/drain region may include a first epitaxial region along at least one sidewall of the source/drain region having a substantially uniform sidewall thickness. The semiconductor structure may further include a gate structure adjacent and above the source/drain region wherein at least a portion of the first epitaxial region is positioned below a sidewall spacer of the gate structure. A method of forming a source/drain region including a first epitaxial region having a substantially uniform sidewall thickness is disclosed. The method may include forming a trench in a substrate adjacent to a gate structure, forming the first epitaxial region in the trench, forming a spacer material layer on the gate structure and on a portion of the first epitaxial region, and removing a portion of the first epitaxial region using the spacer material layer as a mask.
    Type: Application
    Filed: November 14, 2017
    Publication date: May 16, 2019
    Inventors: Yoong Hooi Yong, Yanping Shen, Hsien-Ching Lo, Xusheng Wu, Joo Tat Ong, Wei Hong, Yi Qi, Dongil Choi, Yongjun Shi, Alina Vinslava, James Psillas, Hui Zang
  • Publication number: 20190131432
    Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region beneath a top surface of a semiconductor fin. The semiconductor fin is etched with an anisotropic etching process to form a cavity having a sidewall with a planar section extending vertically toward the top surface of the semiconductor fin and adjacent to the channel region in the semiconductor fin. The semiconductor fin is then etched with an isotropic etching process that widens the cavity at the top surface while preserving verticality of the planar section.
    Type: Application
    Filed: October 27, 2017
    Publication date: May 2, 2019
    Inventors: Yi Qi, Sang Woo Lim, Kyung-Bum Koo, Alina Vinslava, Pei Zhao, Zhenyu Hu, Hsien-Ching Lo, Joseph F. Shepard, JR., Shesh Mani Pandey
  • Publication number: 20190131433
    Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a first cavity extending into the semiconductor fin adjacent to the channel region. The semiconductor fin is etched with a second etching process to form a second cavity that is volumetrically smaller than the first cavity and that adjoins the first cavity.
    Type: Application
    Filed: October 27, 2017
    Publication date: May 2, 2019
    Inventors: Alina Vinslava, Hsien-Ching Lo, Yongjun Shi, Jianwei Peng, Jianghu Yan, Yi Qi