Abstract: A programmable memory transistor (PMT) comprising an IGFET and a coupling capacitor in a semiconductor substrate. The IGFET comprises source and drain regions, a channel therebetween, a gate insulator overlying the channel, and a first floating gate over the gate insulator. The capacitor comprises a lightly-doped well of a first conductivity type, heavily-doped contact and injecting diffusions of opposite conductivity types in the lightly-doped well, a control gate insulator overlying a surface region of the lightly-doped well between the contact and injecting diffusions, a second floating gate on the control gate insulator, and a conductor contacting the lightly-doped well through the contact and injecting diffusions. The first and second floating gates are preferably patterned from a single polysilicon layer, such that the second floating gate is capacitively coupled to the lightly-doped well, and the latter defines a control gate for the first floating gate.

Abstract: A programmable memory transistor (PMT) comprising an IGFET and a coupling capacitor in a semiconductor substrate. The IGFET comprises source and drain regions, a channel therebetween, a gate insulator overlying the channel, and a first floating gate over the gate insulator. The capacitor comprises a lightly-doped well of a first conductivity type, heavily-doped contact and injecting diffusions of opposite conductivity types in the lightly-doped well, a control gate insulator overlying a surface region of the lightly-doped well between the contact and injecting diffusions, a second floating gate on the control gate insulator, and a conductor contacting the lightly-doped well through the contact and injecting diffusions. The first and second floating gates are preferably patterned from a single polysilicon layer, such that the second floating gate is capacitively coupled to the lightly-doped well, and the latter defines a control gate for the first floating gate.

Abstract: A glass envelope contains a silicon substrate which embodies an active matrix anode array, a microprocessor, and anode driving circuits. A small number of pins on the envelope couple display parameters and control signals to the microprocessor, and logic and anode signal voltages are supplied to the substrate. The microprocessor determines which pixels in the anode array should be energized and the driving circuit addresses the array and applies energizing voltage to the selected pixels. The driving circuit is supplied by the low signal voltage and includes a voltage level shifting function to increase the level by an order of magnitude to realize a voltage high enough for adequate display brightness. The display can be made small due to the small number of pins required.

Abstract: A single glass envelope contains fixed anode segments on the glass surface and a silicon substrate mounted on the same surface. The silicon substrate contains an active matrix vacuum fluorescent anode array as well as serial interface circuitry and a driver circuit for each of the AMVFD and the fixed segment display to minimize the number of input pins in the lead frame of the envelope. Aluminum traces on the glass surface are wire bonded to the substrate and extend to the fixed segments and to the lead frame pins.