Abstract: Data processing apparatus comprises one or more transaction issuing devices configured to issue data processing transactions to be handled by a downstream device and to receive a completion acknowledgement in respect of each completed transaction; each transaction issuing device having associated transaction regulator circuitry configured to allow that transaction issuing device to issue transactions subject to a limit on a maximum number of outstanding transactions, an outstanding transaction being a transaction which has been issued but for which a completion acknowledgement has not yet been received; in which the downstream device is configured to issue an indication to a transaction issuing device, to authorize a change by the transaction regulator circuitry of the limit applicable to outstanding transactions by that transaction issuing device.

Abstract: Data processing apparatus comprises one or more transaction issuing devices configured to issue data processing transactions to be handled by a downstream device and to receive a completion acknowledgement in respect of each completed transaction; each transaction issuing device having associated transaction regulator circuitry configured to allow that transaction issuing device to issue transactions subject to a limit on a maximum number of outstanding transactions, an outstanding transaction being a transaction which has been issued but for which a completion acknowledgement has not yet been received; in which the downstream device is configured to issue an indication to a transaction issuing device, to authorise a change by the transaction regulator circuitry of the limit applicable to outstanding transactions by that transaction issuing device.

Abstract: An arbiter is configured to select one of several contending data packets transmitted from an initiator, the data packets comprising an identifier identifying the initiator and data. The arbiter comprises: a history buffer for storing the identifiers identifying the initiators of a plurality of recently selected data packets; and selection circuitry configured to select one of the contending data packets in dependence upon the initiators of the contending data packets and the initiators identified in the history buffer, such that a probability of a data packet being selected increases with the number of data packets selected since a data packet from the same initiator was selected.

Abstract: A data processing apparatus is provided with a master device and a slave device which communicate via communication circuitry. The slave device is associated with a predetermined number of permission tokens that is equal to a maximum number of currently pending messages that can be accepted for processing from the communication circuitry by that slave device. The slave device transmits these permission tokens to the master device. The master device takes exclusive temporary possession of the permission tokens that it receives such that the permission tokens are then no longer available to any other master device. A master device initiates a message to a slave device when the master device has exclusive temporary possession of a permission token for that slave device. When the master device has initiated its message, then it relinquishes the exclusive temporary possession of the permission token such that it is then available for other devices.

Abstract: A data processing apparatus is provided with a master device and a slave device which communicate via communication circuitry. The slave device is associated with a predetermined number of permission tokens that is equal to a maximum number of currently pending messages that can be accepted for processing from the communication circuitry by that slave device. The slave device transmits these permission tokens to the master device. The master device takes exclusive temporary possession of the permission tokens that it receives such that the permission tokens are then no longer available to any other master device. A master device initiates a message to a slave device when the master device has exclusive temporary possession of a permission token for that slave device. When the master device has initiated its message, then it relinquishes the exclusive temporary possession of the permission token such that it is then available for other devices.

Abstract: Buffer circuitry 14 is provided with shared buffer circuitry 20 which stores, in order of reception time, data transaction requests received from one or more data transaction sources. The buffer circuitry 14 operates in either a bypass mode or a non-bypass mode. When operating in the bypass mode, any low latency data transaction requests stored within the shared buffer circuitry are selected in order for output in preference to data transaction requests that are not low latency data transaction requests. In the non-bypass mode, transactions (whether or not they are low latency transactions) are output from the shared buffer circuitry 20 in accordance with the order in which they are received into the shared buffer circuitry 20. The switch between the bypass mode and the non-bypass mode is made in dependence upon comparison of a detected rate of output of low latency data transaction requests compared to a threshold value.

Abstract: An arbiter is configured to select one of several contending data packets transmitted from an initiator, the data packets comprising an identifier identifying the initiator and data. The arbiter comprises: a history buffer for storing the identifiers identifying the initiators of a plurality of recently selected data packets; and selection circuitry configured to select one of the contending data packets in dependence upon the initiators of the contending data packets and the initiators identified in the history buffer, such that a probability of a data packet being selected increases with the number of data packets selected since a data packet from the same initiator was selected.

Abstract: An apparatus and method are provided for performing verification tests for a design of a data processing system. The apparatus comprises a system under verification representing at least part of the design of the data processing system, and a transactor for connecting to an interface of the system under verification, and for generating signals for input to the system under verification via the interface during performance of the verification tests. Profile storage stores a profile providing a statistical representation of desired traffic flow at the interface, the statistical representation providing statistical information for a plurality of traffic attributes and also identifying at least one dependency between such traffic attributes. The transactor then references the profile in order to determine the signals to be generated, such that the signals generated take account of the specified dependencies identified in the profile.

Abstract: An integrated circuit includes a signal source and a signal destination linked by a signal path. Error correction codes (e.g. Hamming codes) are applied to the signals to be transmitted. Errors detected in the signal transmission are used to control an operating parameter of the signal path, such as signal voltage level, body bias voltage, clock frequency and/or temperature. The control applied is closed-loop feedback control seeking to maintain a finite non-zero predetermined error rate. The technique can also be used between a memory accessing integrated circuit and a separate memory integrated circuit. Furthermore, the technique can be used to provide fixed, but differing operating parameters for signal lines within a signal path.

Abstract: A data processing apparatus and method for measuring a value of a predetermined property of transactions are provided. The data processing apparatus has initiator circuitry for initiating transactions, recipient circuitry for handling each transaction initiator by the initiator circuitry, and a communication path interconnecting the initiator circuitry and the recipient circuitry via which the transactions are propagated between the initiator circuitry and the recipient circuitry. Measurement circuitry is coupled to the communication path for measuring a value of a predetermined property of the transactions, such as the latency of those transactions. The measurement circuitry has active transaction count circuitry for maintaining an indication of the number of transactions in progress, and accumulator circuitry for maintaining an accumulator value which is increased dependent on the number of transactions in progress.

Abstract: A bus interconnect device is provided comprising a parallel plate waveguide for coupling together a plurality of devices. This provides an efficient and flexible approach for providing interconnect functionality within a data processing apparatus.

Abstract: A data processing apparatus, bus logic and method are provided for controlling power consumption within a data processing apparatus. The data processing apparatus has a plurality of logic elements, at least one of the logic elements being an initiator logic element for initiating transfers, and at least one of the logic elements being a recipient logic element for receiving transfers. A communication path is provided between an initiator logic element and a recipient logic element to enable payload data the subject of a transfer to be passed from the initiator logic element to the recipient logic element. The communication path has at least one buffer circuit provided therein for propagating at least the payload data along the communication path. Further, a power control circuit is associated with the at least one buffer circuit, which is responsive to a control signal indicating whether the payload data on the communication path is valid.

Abstract: A memory controller includes a write data cache, a read data cache and coherency circuitry. The coherency circuitry manages coherency of data between the write data cache, the read data cache and data stored within a main memory when servicing read requests and write requests received by the memory controller. Write complete signals are issued back to a write requesting circuit as soon as a write request has had its write data stored within the write data cache.

Abstract: An apparatus and method are provided for performing verification tests for a design of a data processing system. The apparatus comprises a system under verification representing at least part of the design of the data processing system, and a transactor for connecting to an interface of the system under verification, and for generating signals for input to the system under verification via the interface during performance of the verification tests. Profile storage stores a profile providing a statistical representation of desired traffic flow at the interface, the statistical representation providing statistical information for a plurality of traffic attributes and also identifying at least one dependency between such traffic attributes. The transactor then references the profile in order to determine the signals to be generated, such that the signals generated take account of the specified dependencies identified in the profile.

Abstract: A data processing apparatus and method for measuring a value of a predetermined property of transactions are provided. The data processing apparatus has initiator circuitry for initiating transactions, recipient circuitry for handling each transaction initiator by the initiator circuitry, and a communication path interconnecting the initiator circuitry and the recipient circuitry via which the transactions are propagated between the initiator circuitry and the recipient circuitry. Measurement circuitry is coupled to the communication path for measuring a value of a predetermined property of the transactions, such as the latency of those transactions. The measurement circuitry has active transaction count circuitry for maintaining an indication of the number of transactions in progress, and accumulator circuitry for maintaining an accumulator value which is increased dependent on the number of transactions in progress.

Abstract: An adaptor circuit 20 for peripheral devices 14, 18 is provided with a direct memory access manager 38. This local direct memory access manager 38 is able to autonomously manage data transfers on behalf of its associated peripheral device 14, 18. A computer program tools used to generate signal interconnects 24 is used to additionally specify whether a DMA capability is to be provided for a peripheral device 14, 18, whereupon an adaptor circuit 20, 22 including a DMA manager 38 can be included within the signal interconnect. A DMA command signal is added to the interconnect signals being passed around the signal interconnect 24 and enables DMA command/configuration data to be distributed using the existing signal distribution infrastructure and addressed to the associated peripheral device 14, 18 of the target local DMA controller 38.

Abstract: A data processing apparatus and method are providing for arbitrating access to a shared resource. The data processing apparatus has a plurality of logic elements sharing access to the shared resource, and arbitration circuitry which is responsive to requests by one or more of the logic elements for access to the shared resource to perform a priority determination operation to select one of the requests as a winning request. The arbitration circuitry applies an arbitration policy to associate priorities with each logic element, the arbitration policy comprising multiple priority groups, each priority group having a different priority and containing at least one of the logic elements. Within each priority group, the arbitration circuitry applies a priority ordering operation to attribute relative priorities to the logic elements within that priority group.

Abstract: A data processing apparatus, bus logic and method are provided for controlling power consumption within a data processing apparatus. The data processing apparatus has a plurality of logic elements, at least one of the logic elements being an initiator logic element for initiating transfers, and at least one of the logic elements being a recipient logic element for receiving transfers. A communication path is provided between an initiator logic element and a recipient logic element to enable payload data the subject of a transfer to be passed from the initiator logic element to the recipient logic element. The communication path has at least one buffer circuit provided therein for propagating at least the payload data along the communication path. Further, a power control circuit is associated with the at least one buffer circuit, which is responsive to a control signal indicating whether the payload data on the communication path is valid.

Abstract: An integrated circuit (2) includes a signal source (4, 6) and a signal destination (10, 12) linked by a signal path (8). Error correction codes (e.g. Hamming codes) are applied to the signals to be transmitted. Errors detected in the signal transmission are used to control an operating parameter of the signal path, such as signal voltage level, body bias voltage, clock frequency and/or temperature. The control applied is closed-loop feedback control seeking to maintain a finite non-zero predetermined error rate. The technique can also be used between a memory accessing integrated circuit (54) and a separate memory integrated circuit (56). Furthermore, the technique can be used to provide fixed, but differing operating parameters for signal lines within a signal path.

Abstract: A bus interconnect device is provided comprising a parallel plate waveguide for coupling together a plurality of devices. This provides an efficient and flexible approach for providing interconnect functionality within a data processing apparatus.