Patents by Inventor Allan Gu
Allan Gu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11301982Abstract: A method includes identifying a first geometric pattern that failed a design rule check, identifying a second geometric pattern that passed the design rule check, morphing the first geometric pattern based on the second geometric pattern to generate a morphed geometric pattern, wherein the morphed geometric pattern passes the design rule check, and replacing the first geometric pattern with the morphed geometric pattern.Type: GrantFiled: August 30, 2019Date of Patent: April 12, 2022Assignee: Intel CorporationInventors: Bikram Baidya, Hale Erten, Allan Gu, John A. Swanson, Vivek K. Singh, Abde Ali Hunaid Kagalwalla, Mengfei Yang-Flint
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Patent number: 11244440Abstract: A method includes, for each data object of a plurality of data objects, performing a measurement on a plurality of instances of the data object to generate a plurality of measurement values for the data object, and generating a distribution of the measurement values for the data object. The method further includes generating an aggregate distribution based on each of the distributions of the measurement values generated for the data objects, and scoring a first data object of the plurality of data objects based on the distribution of the measurement values for the first data object and the aggregate distribution.Type: GrantFiled: August 30, 2019Date of Patent: February 8, 2022Assignee: Intel CorporationInventors: Bikram Baidya, Allan Gu, Vivek K. Singh, Abde Ali Hunaid Kagalwalla
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Patent number: 11176658Abstract: A method comprising determining a binary classification value for each of a plurality of data instances based on a first threshold value assigned to each of the plurality of data instances; applying at least one clustering model to a first subset of the plurality of data instances to identify one or more dominant clusters of data instances; determining a second threshold value to assign to a second plurality of data instances that are included within the one or more dominant clusters of data instances; and redetermining a binary classification value for each of the plurality of data instances based on the second threshold value assigned to the second plurality of data instances and the first threshold value, wherein the first threshold value is assigned to at least a portion of data instances of the plurality of data instances that are not included in the second plurality of data instances.Type: GrantFiled: September 16, 2019Date of Patent: November 16, 2021Assignee: Intel CorporationInventors: Bikram Baidya, Allan Gu, Vivek K. Singh, Kumara Sastry, Abde Ali Hunaid Kagalwalla
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Patent number: 10915691Abstract: A semantic pattern extraction system can distill tremendous amounts of silicon wafer manufacturing data to generate a small set of simple sentences (semantic patterns) describing physical design geometries that may explain manufacturing defects. The system can analyze many SEM images for manufacturing defects in areas of interest on a wafer. A tagged continuous itemset is generated from the images, with items comprising physical design feature values corresponding to the areas of interest and tagged with the presence or absence of a manufacturing defect. Entropy-based discretization converts the continuous itemset into a discretized one. Frequent set mining identifies a set of candidate semantic patterns from the discretized itemset. Candidate semantic patterns are reduced using reduction techniques and are scored. A ranked list of final semantic patterns is presented to a user. The final semantic patterns can be used to improve a manufacturing process.Type: GrantFiled: June 28, 2019Date of Patent: February 9, 2021Assignee: Intel CorporationInventors: Bikram Baidya, Vivek K. Singh, Allan Gu, Abde Ali Hunaid Kagalwalla, Saumyadip Mukhopadhyay, Kumara Sastry, Daniel L. Stahlke, Kritika Upreti
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Publication number: 20200013161Abstract: A method comprising determining a binary classification value for each of a plurality of data instances based on a first threshold value assigned to each of the plurality of data instances; applying at least one clustering model to a first subset of the plurality of data instances to identify one or more dominant clusters of data instances; determining a second threshold value to assign to a second plurality of data instances that are included within the one or more dominant clusters of data instances; and redetermining a binary classification value for each of the plurality of data instances based on the second threshold value assigned to the second plurality of data instances and the first threshold value, wherein the first threshold value is assigned to at least a portion of data instances of the plurality of data instances that are not included in the second plurality of data instances.Type: ApplicationFiled: September 16, 2019Publication date: January 9, 2020Inventors: Bikram Baidya, Allan Gu, Vivek K. Singh, Kumara Sastry, Abde Ali Hunaid Kagalwalla
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Publication number: 20200005451Abstract: A method includes, for each data object of a plurality of data objects, performing a measurement on a plurality of instances of the data object to generate a plurality of measurement values for the data object, and generating a distribution of the measurement values for the data object. The method further includes generating an aggregate distribution based on each of the distributions of the measurement values generated for the data objects, and scoring a first data object of the plurality of data objects based on the distribution of the measurement values for the first data object and the aggregate distribution.Type: ApplicationFiled: August 30, 2019Publication date: January 2, 2020Applicant: Intel CorporationInventors: Bikram Baidya, Allan Gu, Vivek K. Singh, Abde Ali Hunaid Kagalwalla
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Publication number: 20190385300Abstract: A method includes identifying a first geometric pattern that failed a design rule check, identifying a second geometric pattern that passed the design rule check, morphing the first geometric pattern based on the second geometric pattern to generate a morphed geometric pattern, wherein the morphed geometric pattern passes the design rule check, and replacing the first geometric pattern with the morphed geometric pattern.Type: ApplicationFiled: August 30, 2019Publication date: December 19, 2019Applicant: Intel CorporationInventors: Bikram Baidya, Hale Erten, Allan Gu, John A. Swanson, Vivek K. Singh, Abde Ali Hunaid Kagalwalla, Mengfei Yang-Flint
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Publication number: 20190318059Abstract: A semantic pattern extraction system can distill tremendous amounts of silicon wafer manufacturing data to generate a small set of simple sentences (semantic patterns) describing physical design geometries that may explain manufacturing defects. The system can analyze many SEM images for manufacturing defects in areas of interest on a wafer. A tagged continuous itemset is generated from the images, with items comprising physical design feature values corresponding to the areas of interest and tagged with the presence or absence of a manufacturing defect. Entropy-based discretization converts the continuous itemset into a discretized one. Frequent set mining identifies a set of candidate semantic patterns from the discretized itemset. Candidate semantic patterns are reduced using reduction techniques and are scored. A ranked list of final semantic patterns is presented to a user. The final semantic patterns can be used to improve a manufacturing process.Type: ApplicationFiled: June 28, 2019Publication date: October 17, 2019Inventors: Bikram Baidya, Vivek K. Singh, Allan Gu, Abde Ali Hunaid Kagalwalla, Saumyadip Mukhopadhyay, Kumara Sastry, Daniel L. Stahlke, Kritika Upreti
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Patent number: 8201110Abstract: Optical proximity correction (OPC) is a technique used to compensate for optical distortions, process effects, or both, by modifying a pattern that is used during lithography. A reference OPC model is used to create an OPC design layout pattern based on pre-distorting a desired design layout pattern associated with an integrated circuit (IC). The OPC design layout pattern is used when the IC is produced, such that the fabricated IC ideally matches the desired design layout pattern. The present invention relates to using a regression OPC model to create estimated fragment movements of the desired design layout pattern. The estimated fragment movements are then provided as initial fragment movements to the reference OPC model, which then creates the OPC design layout pattern. The initial fragment movements provided by the regression OPC model may reduce the number of iterations needed by the reference OPC model, thereby reducing computation time.Type: GrantFiled: April 14, 2009Date of Patent: June 12, 2012Assignee: The Regents of the University of CaliforniaInventors: Allan Gu, Avideh Zakhor, Peiran Gao