Abstract: Systems for improvising sensorimotor function of a patient, wherein the various systems can include at least one force and/or pressure sensor associated with at least one lower limb or prosthesis of the patient, at least one motion and/or angle sensor associated with at least one lower limb or prosthesis of the patient, a processor configured to receive force and/or pressure signals and motion and/or angle signals and generate an estimated center of pressure and a center of gravity, and generate balance stimulation signals based on the estimated center of pressure and the center of gravity, and at least one sensory stimulation unit disposed on at least one lower limb or prosthesis of the patient, wherein the at least one sensory stimulation unit comprises at least two stimulators that are actuable to provide stimulation to the patient based on the balance stimulation signals.

Abstract: A computer implemented method, data processing system, and computer usable program code are provided for using identifier virtualization to extend the virtualization capabilities of protocols. A determination is made as to whether a logical entity requires a unique identifier in order to extend a virtualization capability of a protocol. A unique name is assigned that is associated with the logical entity. The unique identifier is requested from a fabric using the unique name. The logical entity is notified that the unique identifier has been established for the logical entity in response to receiving the unique identifier from the fabric. The unique identifier identifies the logical entity within or attached to the fabric.

Abstract: A computer implemented method, data processing system, and computer usable program code are provided for using identifier virtualization to extend the virtualization capabilities of protocols. A determination is made as to whether a logical entity requires a unique identifier in order to extend a virtualization capability of a protocol. A unique name is assigned that is associated with the logical entity. The unique identifier is requested from a fabric using the unique name. The logical entity is notified that the unique identifier has been established for the logical entity in response to receiving the unique identifier from the fabric. The unique identifier identifies the logical entity within or attached to the fabric.

Abstract: An apparatus, system and method for providing multiple logical partitions in a system area network are provided Logical partitioning support is provided for host channel adapters which allows multiple operating systems to share the resources of a single physical host channel adapter (HCA). The apparatus, system and method ensures that each operating system is unaware that the HCA hardware resources are being shared with other operating systems and further guarantees that the individual operating systems are prevented from accessing HCA hardware resources which are associated with other operating systems.

Abstract: A system for treating a hydrocarbon containing formation is described. The system includes two or more groups of elongated heaters. The group includes two or more heaters placed in two or more openings in the formation. The heaters in the group are electrically coupled below the surface of the formation. The openings include at least partially uncased wellbores in a hydrocarbon layer of the formation. The groups are electrically configured such that current flow through the formation between at least two groups is inhibited. The heaters are configured to provide heat to the formation.

Abstract: An apparatus, system and method for providing multiple logical partitions in a system area network are provided Logical partitioning support is provided for host channel adapters which allows multiple operating systems to share the resources of a single physical host channel adapter (HCA). The apparatus, system and method ensures that each operating system is unaware that the HCA hardware resources are being shared with other operating systems and further guarantees that the individual operating systems are prevented from accessing HCA hardware resources which are associated with other operating systems.

Abstract: Disclosed is a system for dynamically assigning alias addresses to base addresses referencing an I/O device, such as a direct access storage device (DASD). In the system, at least one base control block indicates a base address and a plurality of alias control blocks indicate a plurality of alias addresses. Each control block is associated with an address for addressing an I/O device. A processing unit, such as a host computer system, processes at least one alias control block associated with the I/O device and determines a base control block associated with the I/O device with which the alias control blocks are associated. The processing unit then binds at least one alias control block to the determined base control block. The bound base and alias control blocks provide different addresses to address the same I/O device.

Abstract: Disclosed is a system for reassigning addresses. A first processing unit, such as a storage controller, provides at least two base addresses for addressing devices, such as volumes of a direct access storage device (DASD) and a plurality of alias addresses. An alias address associated with a base address provides an address for addressing the device addressed by the base address. The first processing unit processes a command transmitted from a second processing unit, such as a host system that accesses the DASD through the storage controller, to reassign an alias address from a first base address to a second base address. The first base address addresses a first device and the second base address addresses a second device. The first processing unit then indicates that the alias address to reassign is not associated with the first base address and is associated with the second base address. The second device addressed by the second base addresses is capable of being addressed by the reassigned alias address.

Abstract: A dynamic switch connects a control unit to a plurality of channels on one or more processors, each processor controlled by an operating system. A logical path scheduler (LPS) within a master operating system in one of the processors contains a path control table which contains an entry for each control unit, system, and logical path combination--each entry indicating current path status (connected or disconnected), and time in that status. I/O requests within the systems for which no path currently exists are queued, and the LPS initiates connections and disconnections for the paths to equitably allocate the maximum number of simultaneous path connections allowed for the control unit, among more than that maximum number of contending channels.