Abstract: A method of preparing an etch solution and thinning semiconductor wafers using the etch solution is proposed. The method includes steps of creating a mixture of hydrofluoric acid, nitric acid, and acetic acid in a solution container in an approximate 1:3:5 ratio; causing the mixture to react with portions of one or more silicon wafers, the portions of the one or more silicon wafers are doped with boron in a level no less than 1×1019 atoms/cm3; collecting the mixture after reacting with the boron doped portions of the one or more silicon wafers; and adding collected mixture back into the solution container to create the etch solution.

Abstract: An apparatus that includes a solution bath of a seasoned solution, the seasoned solution containing a mixture of hydrofluoric acid, nitric acid, and acetic acid; and one or more silicon wafers being suspended in a position above the solution bath, wherein at least a portion of the mixture having been used in thinning the one or more silicon wafers.

Abstract: A method of preparing an etch solution and thinning semiconductor wafers using the etch solution is proposed. The method includes steps of creating a mixture of hydrofluoric acid, nitric acid, and acetic acid in a solution container in an approximate 1:3:5 ratio; causing the mixture to react with portions of one or more silicon wafers, the portions of the one or more silicon wafers are doped with boron in a level no less than 1×1019 atoms/cm3; collecting the mixture after reacting with the boron doped portions of the one or more silicon wafers; and adding collected mixture back into the solution container to create the etch solution.

Abstract: This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a compressive diffusion barrier material. The barrier material preferably has a compressive stress of greater than 300 MPa. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material, then the planarizing material is deposited in the vias and on the dielectric material, and the barrier material is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material, etched through the barrier material into the planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed.

Abstract: This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a compressive diffusion barrier material. The barrier material preferably has a compressive stress of greater than 300 MPa. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material, then the planarizing material is deposited in the vias and on the dielectric material, and the barrier material is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material, etched through the barrier material into the planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed.

Abstract: The present invention relates generally to the field of semiconductor device manufacturing, and more specifically to an apparatus and method for in-situ cleaning of a throttle valve in a chemical vapor deposition (CVD) system. In the exhaust flow control apparatus of the CVD system, which comprises a chamber isolation valve, throttle valve and vacuum pump, means are provided for introducing cleaning gases downstream of the chamber isolation valve and upstream of the throttle valve. Such means may include a cleaning isolation valve connected to a cleaning gas source. Means for generating a reactive plasma of the cleaning gases, just before the throttle valve, may also be provided. During cleaning of the throttle valve, the CVD chamber is isolated, by closing the chamber isolation valve, and cleaning gases are flowed into the throttle valve, by opening the cleaning isolation valve.

Abstract: The present invention relates generally to the field of semiconductor device manufacturing, and more specifically to an apparatus and method for in-situ cleaning of a throttle valve in a chemical vapor deposition (CVD) system. In the exhaust flow control apparatus of the CVD system, which comprises a chamber isolation valve, throttle valve and vacuum pump, means are provided for introducing cleaning gases downstream of the chamber isolation valve and upstream of the throttle valve. Such means may include a cleaning isolation valve connected to a cleaning gas source. Means for generating a reactive plasma of the cleaning gases, just before the throttle valve, may also be provided. During cleaning of the throttle valve, the CVD chamber is isolated, by closing the chamber isolation valve, and cleaning gases are flowed into the throttle valve, by opening the cleaning isolation valve.