Abstract: A cache memory architecture, a method of operating a cache memory and a memory controller. In one embodiment, the cache memory architecture includes: (1) a segment memory configured to contain at least one most significant bit (MSB) of a main memory address, the at least one MSB being common to addresses in a particular main memory logical segment that includes the main memory address, (2) a tag memory configured to contain tags that include other bits of the main memory address and (3) combinatorial logic associated with the segment memory and the tag memory and configured to indicate a cache hit only when both the at least one most significant bit and the other bits match a requested main memory address.

Abstract: An apparatus comprising a plurality of memory modules and a plurality of memory controllers. The plurality of memory modules may be configured to store video data in a half-macroblock organization. Each of the plurality of memory controllers is generally associated with one of the memory modules. The memory controllers are generally configured to index a fetch of pixel data for an unaligned macroblock from the plurality of memory modules.

Abstract: A method for performing multiple-operand logical operations in a single instruction includes the steps of: generating a table defining a correspondence between a plurality of input variables to a multiple-operand logical operation and a plurality of output results of the multiple-operand logical operation; encoding the table to generate a set of values for use by the single instruction, each value being indicative of an output result of the multiple-operand logical operation as a function of a corresponding unique combination of values of the input variables; and at least one processor performing the multiple-operand logical operation in a single instruction as a function of the set of values for a prescribed combination of values of the input variables.

Abstract: A cache memory architecture, a method of operating a cache memory and a memory controller. In one embodiment, the cache memory architecture includes: (1) a segment memory configured to contain at least one most significant bit (MSB) of a main memory address, the at least one MSB being common to addresses in a particular main memory logical segment that includes the main memory address, (2) a tag memory configured to contain tags that include other bits of the main memory address and (3) combinatorial logic associated with the segment memory and the tag memory and configured to indicate a cache hit only when both the at least one most significant bit and the other bits match a requested main memory address.

Abstract: A bus termination scheme that minimizes signal reflection and that minimizes the effect of the number of devices coupled to the bus. In this invention, a resistor is provided between a signal driver and the transmission bus. In addition, a resistance is provided between the bus and each receiving means. The driver resistor reduces the effective capacitance of the transmission line as well as effectively source terminating the line. The receiver resistor reduces effective capacitance and damps signal reflections. Thus, the performance of the bus is increased by minimizing the effects of the number of drivers and receivers on the bus. In addition, the drivers can be lower powered than prior art drivers because no static and a reduced dynamic load is presented to the driver. Finally, the resistors do not dissipate power continuously but only when a transmitter changes the bus state or potential, further enhancing low power operation.

Abstract: A bus termination scheme that minimizes signal reflection and that minimizes the effect of the number of devices coupled to the bus. In this invention, a resistor is provided between a signal driver and the transmission bus. In addition, a resistance is provided between the bus and each receiving means. The driver resistor reduces the effective capacitance of the transmission line as well as effectively source terminating the line. The receiver resistor reduces effective capacitance and damps signal reflections. Thus, the performance of the bus is increased by minimizing the effects of the number of drivers and receivers on the bus. In addition, the drivers can be lower powered than prior art drivers because no static and a reduced dynamic load is presented to the driver. Finally, the resistors do not dissipate power continuously but only when a transmitter changes the bus state or potential, further enhancing low power operation.

Abstract: A process for fairly allocating resources in a multiport packet switch is disclosed. Each port is connected to a station and comprises a transmit FIFO buffer and a receive FIFO buffer. The ports are connected by a broadcast transmission medium. A transmit buffer of a specific port gains access to the transmission medium when the port possesses a token which is passed from port to port in a round-robin fashion. When a port recognizes that a transmitted packet is addressed to it, the port uses a local processor to determine whether or not to accept the packet. The determination is based on (1) information in the packet header, e.g., priority and address of the transmitting port, (2) the status of the receive buffer (full or not), and (3) other locally recorded information regarding past history of the acceptance or rejection of packets from particular ports and of particular priority classes needed to achieve fairness among packets of the same class and priority among different classes.