Abstract: During a method for generating a mask pattern for a photo-mask, a target pattern is partitioned into subsets of the target pattern. The subsets of the target pattern may be selected so that at least some of the subsets are approximately identical, thereby dividing the subsets into a degenerate group and a non-degenerate group. A group of the subsets may include multiple shapes, and a given target pattern may be significantly larger than a pre-determined length scale and a given shape in the multiple shapes is smaller than the pre-determined length scale. The non-degenerate group of subsets of the target pattern may be distributed to multiple processors. These processors may be used to determine subsets of the mask pattern based on the non-degenerate group of subsets of the target pattern. The subsets of the mask pattern may be combined to generate the mask pattern.

Abstract: During a method for generating a mask pattern for a photo-mask, a target pattern is partitioned into subsets of the target pattern. The subsets of the target pattern may be selected so that at least some of the subsets are approximately identical, thereby dividing the subsets into a degenerate group and a non-degenerate group. A group of the subsets may include multiple shapes, and a given target pattern may be significantly larger than a pre-determined length scale and a given shape in the multiple shapes is smaller than the pre-determined length scale. The non-degenerate group of subsets of the target pattern may be distributed to multiple processors. These processors may be used to determine subsets of the mask pattern based on the non-degenerate group of subsets of the target pattern. The subsets of the mask pattern may be combined to generate the mask pattern.

Abstract: A method implemented on a computer system for enhancing performance of an integrated circuit design verification system, the computer system having a memory including a circuit design, the circuit design including a base layer, a first layer, a second layer, a first derived layer, and a second derived layer, the first derived layer defined in response to operation between the base layer and the first layer, the second derived layer defined in response to an operation between the second layer and the first derived layer, includes the steps of retrieving the first layer from the memory, the first layer located within the base layer, deriving a negative first derived layer in response to the first layer, the negative first derived layer being a negative domain representation of the first derived layer, and verifying the circuit design in response to the negative first derived layer.

Abstract: A system for model-based verification of local design rules comprises a processing unit, a verification database wherein a cell reference graph representing an integrated circuit design as a hierarchical collection of cells is stored, a verification function memory wherein a verification function is stored, a friendly worklayer memory, and an unfriendly worklayer memory. Each cell can include shape models and references to lower-level cells. The processing unit first verifies each cell in the cell reference graph that does not reference any lower-level cells, after which the processing unit verifies each cell for which all lower-level cells referenced have been previously verified. During the verification of a selected cell, the processing unit determines whether models in the selected cell interact with other models in the selected cell or with any lower-level cell. Interacting models are referred to as being "unfriendly," and non-interacting models are referred to as being "friendly.

Abstract: A method and apparatus to enable the size reduction of geometric databases used in the analysis of integrated circuit layouts. The results of design rule analysis on the groups of polygon shapes comprising the integrated circuit layout are stored as either in-group results or override results in a dedicated result register memory. In-group results are design rule analysis results which contain only shapes contained in the group being analyzed. Override results are additional shape models produced when the spatial relationship between the shapes in the group being analyzed and shapes in lower level groups invalidate the results previously obtained for those lower level groups. The data base structure is created using a general purpose computer consisting of a CPU connected to a plurality of memories along a common data bus.

Abstract: An improved circuit layout-verifying system and method operates on a plurality of polygons that are representative of an electrical node to test the proper or improper connection of each polygon to another contiguous polygon and designates for display those polygons that represent improper connections between known or identified reference points on the node. Traversals along a sequence of contiguous polygons between known reference points on the same electrical node are designated as proper connections or successes, and traversals along a sequence of contiguous polygon between reference points associated with different electrical nodes are designated as improper connections or failures at least along a portion of the sequence. Data from all traversals of all polygons from all known reference points is then analyzed to remove unambiguous sequences of polygons for the improperly connected electrical nodes.