Abstract: A multiprocessor interrupt rerouting mechanism and method is disclosed for rerouting messages intended for a first processor to a second processor. In a fault tolerant computer system having several processors or LANs under the control of a single controller, when the controller completes a communication task requested by one of the processors, it will send an interrupt request to the requesting processor which then notifies the application process for which the communication task was performed, information regarding the status of the communication task. If for any reason the requesting processor being interrupted is inoperative or too busy to handle the interrupt request, the application process is then notified as to the status of the communication task by rerouting the interrupt request from the controller so that another processor can handle it.

Abstract: A local area network (LAN) system is provided that is capable of accommodating a variety of computer subsystem types, and having a LAN controller which can control at substantially the same time a plurality of LANs of the same type or a plurality of different types of LANs.

Abstract: A split bus architecture which separates the processor/processors and the procedure memory coupled to a microprocessor (.mu.P) bus from all direct memory access (DMA) devices coupled to a DMA bus. A coupler mechanism provides bus isolation of the microprocessor bus from the DMA bus and permits the processor to access devices on the DMA side when addressed. This separation allows data transfers to proceed on one side of the bus without interfereing with software execution on the other side of the bus.

Abstract: Local area network control block (LCB) hardware and a method is disclosed which forms a prime vehicle of intercommunication between controller coupled local area networks (LANs), comprising a plurality of computer systems. An LCB has a predetermined format and is assembled by the computer hardware to provide information to the controller regarding the routing and transfer of a variable quantity of data between LANs.

Abstract: A communication multiplexer stores the receive and transmit channel numbers of input/output devices coupled to the multiplexer by communication lines in a first-in-first out (FIFO) memory. The input/output devices are polled by sending the channel numbers from the FIFO to the input/output devices. An input/output device requesting service responds to its channel number. The remaining channel numbers in the FIFO are recirculated to give the receive channel numbers priority over the transmit channel numbers. This gives high priority to a most recently used receive channel operative in a burst mode and equal priority to all transmit channels.

Abstract: A data processing system includes means which are operative when the system is conditioned for operating in a trace mode during the processing of program instructions, to record the op code of each instruction designated as executable by the bit contents of a table referenced before beginning instruction execution. When the op code of an instruction is designated by the table as not being executable, the system traps the instruction and generates a call to the operating system software without recording its op code. The selective recording and trapping of instruction operation codes facilitates diagnosis of program errors or faults within the system. This is particularly valuable when the system includes emulation apparatus which may not be completely compatible in every detail with the system being emulated.

Abstract: A processing unit includes emulation apparatus which operates to execute instructions of a target system, one of a plurality of ways depending upon the options and features of the target system being emulated. The options, features and characteristics of the target system for which the program was originated is defined by the different bits of an option mask word stored within the emulation apparatus. Initially, upon switching to an emulation mode of operation, the emulation apparatus under microprogram control is operative to store signal representations of the option mask word in one of its storage registers. The signals from the stored option mask word are applied to different portions of the emulation apparatus for conditioning the apparatus to execute target system program instructions in accordance with the structural characteristics of the target system for which the program was originated.

Abstract: A host system includes a plurality of memory cells, each reserved for a different one of a plurality of peripheral control devices of a target system. During the running of a target system program, the host system being emulated includes means for switching one of the memory cells reserved for a particular peripheral control upon detection of an interrupt condition resulting from the execution of a target system input/output instruction. Each time an interrupt condition causes the switching of one of these cells, the host system increments by one the contents of a counter representative of a bus present in the target system. Each time one of the cells of a bus is reset or cleared, the host system decrements by one the corresponding counter contents.

Abstract: A host microprogrammed data processing system includes a plurality of tables to store information coded to define a plurality of a variety of different input-output system configurations of resources required to execute input-output instructions in a corresponding number of target systems being emulated by the host system. The host system further includes emulation apparatus which includes a control store which stores microprograms for directing the system in processing input-output instructions of target programs and for verifying whether each such instruction can be executed by the host system. The emulation apparatus generates coded information indicating which one of a given number of channel program routines the host system is required to use to execute the input-output instruction using the host input-output resources. Using the information of the tables, the emulation apparatus is able to execute completely certain types of target system input-output instructions used to perform control operations.