Abstract: A method of reducing jitter in a phase locked loop (PLL) includes receiving a first reference signal, quadrupling a frequency of the first reference signal to produce a second reference signal, and providing the second reference signal to a frequency phase detector of the PLL. The method may also include equalizing the second reference signal prior to providing the second reference signal to the frequency phase detector. The method can be accomplished by a circuit, wherein quadrupling the frequency of the first reference signal is performed by two frequency doublers arranged in series. The step of equalizing can be performed by two equalizers, each one configured to equalize an output of a respective frequency doubler.

Abstract: Circuitry for a phase locked loop (PLL) includes a reference signal input and a frequency doubler. The output of the frequency doubler is a second reference signal having a frequency that is approximately twice that of the initial reference signal, and which is fed into the PLL. The frequency doubler includes a first delay circuit having an input coupled to the input of the frequency doubler; and an XOR circuit having a first input coupled to an output of the delay circuit and a second input coupled to the input of the frequency doubler. The frequency doubler can include one or more additional delay circuits in series after the first delay circuit, the output of which is provided to a multiplexer. The multiplexer includes a selection signal input for selecting an output from at least one of the delay circuits to be provided to the XOR circuit. The frequency doubler allows the PLL to have a smaller feedback divider ratio and a higher loop gain for reducing jitter.

Abstract: A low-jitter phase-locked loop (PLL) circuit includes a reference signal generator and a PLL. The reference signal generator is configured to quadruple a frequency of a first reference signal to produce a second reference signal. The PLL includes a filter coupled in series with a voltage controlled oscillator (VCO), and a frequency phase detector configured to generate a first error signal based on a frequency difference between the second reference signal and a first divided VCO output signal. The PLL further includes a phase detector configured to generate a second error signal based on a phase difference between the second reference signal and a second divided VCO output signal at each rising and falling transition of the second reference signal.

Abstract: Circuitry for a phase locked loop (PLL) includes a first frequency doubler; a first equalizer having an input coupled to an output of the first frequency doubler; a second frequency doubler having an input coupled to an output of the first equalizer; and a second equalizer having an input coupled to an output of the second frequency doubler and an output which is fed into the PLL. Each frequency doubler includes a first delay circuit having an input coupled to the input of the frequency doubler; and an XOR circuit having a first input coupled to an output of the delay circuit and a second input coupled to the input of the frequency doubler. The combination of the two frequency doublers in series quadruples the reference signal into the PLL, which allows the, PLL to have a smaller feedback divider ratio and a higher loop gain for reducing jitter. Advantageously, controls for the selection of the initial reference signal are provided.

Abstract: A complementary metal-oxide semiconductor (CMOS) integrated circuit that includes a clock recovery circuit. The clock recovery circuit automatically properly aligns a clock with data. A latch is used to perform the function of a flip-flop. Because the flip flop is essentially two latches, using the latch rather than the flip flop results in a circuit having one less latch. Consequently, the circuit has less propagation delay, which permits higher frequency operation. Use of the latch also reduces the load on the clock and saves power. Additionally, the clock recovery circuit uses differential logic, which decreases noise sensitivity and allows higher frequency operation.

Abstract: An integrated circuit complementary metal-oxide silicon (CMOS) voltage controlled oscillator (VCO) includes a plurality of variable delay elements, connected in a ring configuration, each variable delay element including a pair of parallel connected differential CMOS sections. The parallel-connected differential CMOS sections of each variable delay element are controlled by a differential control voltage whose magnitude sets relative levels of operation of the two differential sections of each variable delay element. These relative levels of operation determine the delay through the variable delay element. A current mirror circuit provides the differential control voltage.

Abstract: An integrated circuit complementary metal-oxide silicon (CMOS) voltage controlled oscillator (VCO) includes a plurality of variable delay elements, connected in a ring configuration, each variable delay element including a pair of parallel connected differential CMOS sections. The parallel-connected differential CMOS sections of each variable delay element are controlled by a differential control voltage whose magnitude sets relative levels of operation of the two differential sections of each variable delay element. These relative levels of operation determine the delay through the variable delay element. The control circuit provides the differential control voltage. The control circuit includes a first section for generating a control current and a pair of current mirror sections that divide the control current, generating a pair of differential control signal components as VGS potentials of a pair of CMOS transistors configured as current mirrors.