Abstract: A modified CMOS switch, composed of parallel N-channel and P-channel transistors, is placed between the pad and the input buffer and/or output devices. The applied pad voltage relative to VDD determines the configuration of the switch, and also, the P-channel floating-well bias-voltage. For the applied pad voltage above VDD, only the N-channel device is on and the P-channel device is off. In this configuration the N-channel limits the input voltage on the buffer side to (VDD?VTN), and therefore, acts as the over-voltage protection device. For pad voltages at and below VDD, both the N-channel and the P-channel devices are on, and the voltage-levels on both sides of the protection structure are the same.

Abstract: In an integrated circuit, capacitively coupled interference (digital-switching or analog cross-talk) is prevented by constructing shielded coaxial conductors for the analog signals. The coaxial configuration comprises a primary conductor for the analog signal surrounded by a secondary conductor that is electrically isolated from the primary one and that is connected to a clean power bus such as GND or Vdd. The outer secondary conductor shunts the digital noise energy to the power bus, preventing it from injecting noise into the analog primary conductor. A similar coaxial configuration is provided with a bootstrap follower to reduce the effects of parasitic capacitance for high-speed and small analog signals.