Patents by Inventor Allen K. Lam
Allen K. Lam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7667309Abstract: Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package.Type: GrantFiled: March 14, 2008Date of Patent: February 23, 2010Assignee: GEM Services, Inc.Inventors: James Harnden, Allen K. Lam, Richard K. Williams, Anthony Chia, Chu Weibing
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Patent number: 7485498Abstract: Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package.Type: GrantFiled: February 2, 2007Date of Patent: February 3, 2009Assignee: GEM Services, Inc.Inventors: James Harnden, Allen K. Lam, Richard K. Williams, Anthony Chia, Chu Weibing
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Publication number: 20080217662Abstract: Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package.Type: ApplicationFiled: March 14, 2008Publication date: September 11, 2008Applicant: GEM Services, Inc.Inventors: James Harnden, Allen K. Lam, Richard K. Williams, Anthony Chia, Chu Weibing
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Patent number: 7215012Abstract: Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package.Type: GrantFiled: December 12, 2003Date of Patent: May 8, 2007Assignee: GEM services, Inc.Inventors: James Harnden, Allen K. Lam, Richard K. Williams, Anthony Chia, Chu Weibing
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Patent number: 6800932Abstract: A semiconductor package contains a plurality of sheet metal leads that are attached to one or more terminals on a top side of a semiconductor die. A heat sink is attached to a terminal on a bottom side of the die. Each of the leads extends across the die and beyond opposite edges of the die and is symmetrical about an axis of the die. At the locations where the leads pass over the edges of the die notches are formed on the sides of the leads which face the die, thereby assuring that there is no contact between the leads and the peripheral portion of the top surface of the die. Particularly in power MOSFETs the peripheral portion of the top surface normally contains an equipotential ring which is directly connected to the backside (drain) of the MOSFET, and hence a short between the leads on the top of the die and the equipotential ring would destroy the device. The result is a package that is extremely rugged and that is symmetrical about the axis of the die.Type: GrantFiled: January 30, 2002Date of Patent: October 5, 2004Assignee: Advanced Analogic Technologies, Inc.Inventors: Allen K. Lam, Richard K. Williams, Alex K. Choi
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Publication number: 20040173881Abstract: Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package.Type: ApplicationFiled: December 12, 2003Publication date: September 9, 2004Applicant: GEM Services, Inc.Inventors: James Harnden, Allen K. Lam, Richard K. Williams, Anthony Chia, Chu Weibing
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Patent number: 6452802Abstract: A semiconductor package contains a plurality of sheet metal leads that are attached to one or more terminals on a top side of a semiconductor die. A heat sink is attached to a terminal on a bottom side of the die. Each of the leads extends across the die and beyond opposite edges of the die and is symmetrical about an axis of the die. At the locations where the leads pass over the edges of the die notches are formed on the sides of the leads which face the die, thereby assuring that there is no contact between the leads and the peripheral portion of the top surface of the die. Particularly in power MOSFETs the peripheral portion of the top surface normally contains an equipotential ring which is directly connected to the backside (drain) of the MOSFET, and hence a short between the leads on the top of the die and the equipotential ring would destroy the device. The result is a package that is extremely rugged and that is symmetrical about the axis of the die.Type: GrantFiled: July 2, 2001Date of Patent: September 17, 2002Assignee: Advanced Analogic Technologies, Inc.Inventors: Allen K. Lam, Richard K. Williams, Alex K. Choi
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Publication number: 20020071253Abstract: A semiconductor package contains a plurality of sheet metal leads that are attached to one or more terminals on a top side of a semiconductor die. A heat sink is attached to a terminal on a bottom side of the die. Each of the leads extends across the die and beyond opposite edges of the die and is symmetrical about an axis of the die. At the locations where the leads pass over the edges of the die notches are formed on the sides of the leads which face the die, thereby assuring that there is no contact between the leads and the peripheral portion of the top surface of the die. Particularly in power MOSFETs the peripheral portion of the top surface normally contains an equipotential ring which is directly connected to the backside (drain) of the MOSFET, and hence a short between the leads on the top of the die and the equipotential ring would destroy the device. The result is a package that is extremely rugged and that is symmetrical about the axis of the die.Type: ApplicationFiled: January 30, 2002Publication date: June 13, 2002Inventors: Allen K. Lam, Richard K. Williams, Alex K. Choi
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Publication number: 20010040277Abstract: A semiconductor package contains a plurality of sheet metal leads that are attached to one or more terminals on a top side of a semiconductor die. A heat sink is attached to a terminal on a bottom side of the die. Each of the leads extends across the die and beyond opposite edges of the die and is symmetrical about an axis of the die. At the locations where the leads pass over the edges of the die notches are formed on the sides of the leads which face the die, thereby assuring that there is no contact between the leads and the peripheral portion of the top surface of the die. Particularly in power MOSFETs the peripheral portion of the top surface normally contains an equipotential ring which is directly connected to the backside (drain) of the MOSFET, and hence a short between the leads on the top of the die and the equipotential ring would destroy the device. The result is a package that is extremely rugged and that is symmetrical about the axis of the die.Type: ApplicationFiled: July 2, 2001Publication date: November 15, 2001Inventors: Allen K. Lam, Richard K. Williams, Alex K. Choi
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Patent number: 6307755Abstract: A leadframe for making an electric connection to a semiconductor die contains a plurality of notches which correspond to the edges of the die. Shorts are thereby prevented between the leadframe and electrical elements near the edge of the die, even when the leadframe is bent in the direction of the die to make a surface mount package. Alternatively or additionally, the leads in the leadframe may contain moats which prevent the epoxy or solder used to attach the leadframe to a die from spreading outward and thereby creating electrical shorts with other leads.Type: GrantFiled: May 27, 1999Date of Patent: October 23, 2001Inventors: Richard K. Williams, Allen K. Lam, Alexander K. Choi
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Patent number: 6256200Abstract: A semiconductor package contains a plurality of sheet metal leads that are attached to one or more terminals on a top side of a semiconductor die. A heat sink is attached to a terminal on a bottom side of the die. Each of the leads extends across the die and beyond opposite edges of the die and is symmetrical about an axis of the die. At the locations where the leads pass over the edges of the die notches are formed on the sides of the leads which face the die, thereby assuring that there is no contact between the leads and the peripheral portion of the top surface of the die. Particularly in power MOSFETs the peripheral portion of the top surface normally contains an equipotential ring which is directly connected to the backside (drain) of the MOSFET, and hence a short between the leads on the top of the die and the equipotential ring would destroy the device. The result is a package that is extremely rugged and that is symmetrical about the axis of the die.Type: GrantFiled: May 27, 1999Date of Patent: July 3, 2001Inventors: Allen K. Lam, Richard K. Williams, Alex K. Choi
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Patent number: D505121Type: GrantFiled: January 3, 2003Date of Patent: May 17, 2005Assignee: GEM Services, Inc.Inventors: James Harnden, Richard K. Williams, Anthony Chia, Chu Weibing, Allen K. Lam
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Patent number: D505122Type: GrantFiled: January 3, 2003Date of Patent: May 17, 2005Assignee: GEM Services, Inc.Inventors: James Harnden, Richard K. Williams, Anthony Chia, Chu Weibing, Allen K. Lam
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Patent number: D513608Type: GrantFiled: January 3, 2003Date of Patent: January 17, 2006Assignee: GEM Services, Inc.Inventors: James Harnden, Richard K. Williams, Anthony Chia, Chu Weibing, Allen K. Lam
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Patent number: D485808Type: GrantFiled: January 3, 2003Date of Patent: January 27, 2004Assignee: GEM Services, Inc.Inventors: James Harnden, Richard K. Williams, Anthony Chia, Chu Weibing, Allen K. Lam
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Patent number: D487431Type: GrantFiled: January 3, 2003Date of Patent: March 9, 2004Assignee: GEM Services, Inc.Inventors: James Harnden, Richard K. Williams, Anthony Chia, Chu Weibing, Allen K. Lam
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Patent number: D488136Type: GrantFiled: January 3, 2003Date of Patent: April 6, 2004Assignee: GEM Services, Inc.Inventors: James Harnden, Richard K. Williams, Anthony Chia, Chu Weibing, Allen K. Lam