Abstract: An integrated circuit wafer is formed as a monolithic focal plane array having signal processing circuitry formed upon a first surface thereof and infrared detector elements formed upon a second surface thereof. A process for forming the same is also disclosed. The wafer has an array of waffle-like hollows formed upon one surface. The floor of each hollow has a dense array of small diameter vias formed thereon. The vias extend through the wafer to the second surface thereof. Conductive conduits are formed through the hollows and vias to connect infrared detectors on the second side of the wafer to their associated signal processing circuitry formed upon the first side of the wafer.

Abstract: A stacked integrated circuit assembly [and method of fabricating the same are disclosed. The assembly] includes a plurality of insulating substrate layers each supporting one or more embedded integrated circuit chips. The substrates each incorporate substantially identical conductive patterns formed on the insulating layer surface and/or on an insulating film that covers the substrate.

Abstract: A precisely spaced stack of substrate layers comprises a plurality of substrate layers disposed one above another in a stacked configuration and having a glass layer coating on one of each pair of adjacent substrates, the glass layer having a thickness such that the sum of the thicknesses of the glass layer and the substrate to which the glass layer is fused is approximately equal for substantially all of the substrate layers. A polymer adhesive is disposed intermediate the glass layer and a substrate layer such that adjacent substrate layers are bonded together. By controlling the height of each pair of substrate and glass layers, a precisely spaced and strongly bonded stack of substrate layers is formed.

Abstract: A method for constructing an infrared detector array directly upon a detector interface device is disclosed. The detector interface device mechanically and electrically connects the infrared detector array to signal processing equipment. In a first embodiment of the invention encapsulated single crystalline material is formed within a cavity formed in a substrate. The encapsulated single crystalline material formed within the substrate cavity is suitable for use as a seed crystal for graphotaxial crystal growth of a detector element support layer across the surface of the substrate. Detector elements can then be formed upon the detector element support layer. In a second embodiment of the invention a plurality of detector element support layers can be formed within an array of cavities formed upon the substrate. An individual infrared detector element can then be formed directly upon each of the detector element support layers to form a detector array upon the substrate.

Abstract: A method and construction are disclosed to form a trench gate JFET transistor. The invention comprises forming a first trench in a semiconductor substrate, forming a gate channel about the trench and forming a conductive layer upon the surface of the gate channel. The conductive layer interfaces with the gate channel to form a p-n junction. Source and drain regions are formed adjacent to a trench and disposed in electrical contact with the gate channel. An integral capacitor may be added to the construction by forming a second trench, which extends through and excavates a portion of the first trench. The drain region is extended about the surface of the second trench to remain in electrical contact with the gate channel. A layer of insulating material is applied to the second trench, which is then filled with a body of conductive material. The conductive material is insulated from the conductive layer by the insulating layer.

Abstract: A complimentary trench gate metal-oxide semiconductor transistor is disclosed along with a resulting product. The process for forming the transistor comprises forming a trench within the semiconductor substrate, wherein the semiconductor substrate is doped to a first relative type. A layer doped to a second relative type is applied about the surface of the trench. An insulating layer is then formed within the trench upon said first layer. A region of gate material is formed within the trench upon said insulating layer. Source and drain regions are formed by doping first and second regions adjacent the trench to the opposite relative polarity of the substrate. Segments of the first and second regions are then doped to the same relative polarity as the substrate, the segments being isolated from the substrate by remaining portions of the first and second doped regions.

Abstract: A multilayer integrated circuit module for supporting integrated circuit chips and for interfacing the chips to external circuitry is disclosed. Each integrated circuit is formed to have conductive contact pads disposed upon beveled edges. The module is comprised of a base layer and a plurality of stacked layers having apertures formed therein and disposed upon the base layer such that at least one well is formed. The aperture defining inclined sidewalls with conductive conduits formed thereon. The inclined sidewalls are formed to support the integrated circuit chips upon the beveled surfaces thereof. The conductive conduits formed on the incline sidewalls contact the integrated circuit chip conductive contact pads. The base layer has conductive conduits formed thereon, the base layer further has vertically inclined surfaces spaced to receive and support the integrated circuit chips along beveled edge portions thereof.

Abstract: A method for constructing an infrared detector array directly upon a detector interface device is disclosed. The detector interface device mechanically and electrically connects the infrared detector array to signal processing equipment. In a first embodiment of the invention encapsulated single crystalline material is formed within a cavity formed in a substrate. The encapsulated single crystalline material formed within the substrate cavity is suitable for use as a seed crystal for graphotaxial crystal growth of a detector element support layer across the surface of the substrate. Detector elements can then be formed upon the detector element support layer. In a second embodiment of the invention a plurality of detector element support layers can be formed within an array of cavities formed upon the substrate. An individual infrared detector element can then be formed directly upon each of the detector element support layers to form a detector array upon the substrate.

Abstract: A method of forming an integrated circuit module ae disclosed. The module includes a plurality of integrated circuit layers having beveled vertical edges along a portion thereof. The layers are connected to a contact board disposed orthogonal to the layers and also having a beveled first surface formed to receive and support the integrated circuit layers.

Abstract: A method for forming an array of single crystalline seed crystals separated by an insulator and suitable for use in the formation of infrared detector elements is disclosed. The seed crystals are formed from a single crystalline substrate having first and second planar surfaces. An array of grooves is formed in the first planar surface of the single crystalline substrate such that a plurality of protrusions are formed upon the first planar surface of the single crystalline substrate. The grooves are then filled with an insulator. A portion of the second planar surface of the substrate is then removed to expose the insulator disposed within the grooves to form an array of single crystalline seed crystals. The single crystalline seed crystals are separated by the insulator. The single crystalline seed crystals and the insulator are exposed upon both the first and second surfaces of the array.

Abstract: A process for forming a single trench MOS transistor/capacitor cell for analog signal processing, and the resulting structure, are disclosed. The transistor is formed by foming a first trench in the semiconductor substrate, lining the trench with a layer of insulating material, a layer of conducting material, and filling the trench with a layer of insulator. A doped region is formed adjacent the trench, which serves as a transistor source. A second trench is then formed which extends through and excavates a portion of the first trench. The second trench is lined with a layer of doped material and insulator. The doped material is isolated from the conductive layer lining the first trench. The second trench is then filled with a body of conductive material. The layer of doped material lining the second trench serves as the transistor drain and a capacitor output is extracted from the body of conductive material.

Abstract: A polycrystalline or amorphous substrate having a single crystallilne layer formed thereupon for making a photosensitive detector array and a method for forming the same are disclosed. The single crystalline layer is grown by graphotaxy, i.e. lateral epitaxy, upon the non-single crystalline substrate. A seed crystal of the material which will comprise the layer to be grown is embedded in the substrate. Graphotaxial growth occurs from the seed crystal and travels across the surface of the substrate. Various methods of obtaining graphotaxial growth are disclosed.

Abstract: An infrared detector array which is simultaneously responsive to two different portions of the infrared spectrum is disclosed. The array has detector elements formed upon the two opposite planar surfaces of a substrate. The detector elements formed upon the first surface of the substrate are responsive to a first portion of the infrared spectrum and the detector elements formed upon the second surface of the substrate are responsive to a second portion of the infrared spectrum. An intermediate layer of single crystalline material can be formed upon one or both surfaces of the substrate between the substrate and the dector elements. This intermediate layer of single crystalline material filters infrared radiation not within the second portion of the infrared spectrum to reduce the amount of infraed radiation not within the second portion of the infrared spectrum which is incident upon the detector elements formed upon the second surface of the substrate.

Abstract: A recessed element photosensitive detector array with optical isolation having an increased sensitivity to incident photons and having reduced crosstalk due to low angle of incidence photons is disclosed. The array comprises a substrate, a plurality of parallel elongate cavities formed within the substrate, photosensitive detector elements formed within the cavities, and an optical insulating layer adjacent each of said cavities to optically isolate the cavities from each other. The elongate cavities provide an increased detector element surface area which increases the sensitivity of the recesses element photosensitive detector array to incident photons. The increased sensitivity of the array is due to an increase in the probability of capturing incident photons. The optical isolation provided by the optical insulating layer substantially reduces crosstalk among adjacent detector elements for low angle of incidence photons.

Abstract: A stacked integrated circuit assembly and method of fabricating the same are disclosed. The assembly includes a plurality of insulating substrate layers each supporting one or more embedded integrated circuit chips. The substrates each incorporate substantially identical conductive patterns formed on the insulating layer surface and/or on an insulating film that covers the substrate. A plurality of apertures are then formed which intersect the patterns, followed by insertion of IC chips into the apertures. The insulating layer is then cut to form a plurality of segments which are subsequently stacked vertically to form a module.

Abstract: A detector element signal comparator system is used for noise reduction and image enhancement by comparing the output of any detector signal processor within a module to the output of any other detector signal processor within the same module. The detector element signal comparator system has a comparator for each detector signal processor, a comparator bus to connect the output of any detector signal processor to the comparators of all other detector signal processors, a switch for each detector signal processor to selectively connect each detector signal processor to the comparator bus, and an output bus for communicating the comparator signal from the detector element signal comparator to the next stage of signal processing.

Abstract: A method and construction are disclosed to form a trench gate JFET transistor. The invention comprises forming a first trench in a semiconductor substrate, forming a gate channel about the trench and forming a conductive layer upon the surface of the gate channel. The conductive layer interfaces with the gate channel to form a p-n junction. Source and drain regions are formed adjacent to a trench and disposed in electrical contact with the gate channel. An integral capacitor may be added to the construction by forming a second trench, which extends through and excavates a portion of the first trench. The drain region is extended about the surface of the second trench to remain in electrical contact with the gate channel. A layer of insulating material is applied to the second trench, which is then filled with a body of conductive material. The conductive material is insulated from the conductive layer by the insulating layer.

Abstract: An integrated circuit module and technique for forming the same are disclosed. The module includes a plurality of integrated circuit layers having beveled vertical edges along a portion thereof. The layers are connected to a contact board disposed orthogonal to the layers and also having a beveled first surface formed to receive and support the integrated circuit layers.

Abstract: A polycrystalline or amorphous substrate having a single crystalline layer formed thereupon for making a photosensitive detector array and a method for forming the same are disclosed. The single crystalline layer is grown by graphotaxy, i.e. lateral epitaxy, upon the non-single crystalline substrate. A seed crystal of the material which will comprise the layer to be grown is embedded in the substrate. Graphotaxial growth occurs from the seed crystal and travels across the surface of the substrate. Various methods of obtaining graphotaxial growth are disclosed.

Abstract: A process for bonding electrical terminals of an integrated circuit chip to conductive regions of a multilayered circuit board is disclosed, along with the resulting multilayer module. The process comprises forming a plurality of circuit board layers and stacking them to define a well area therein. The well area having a base defined by one of the circuit board layers and sidewalls defined by vertical edge portions of a plurality of the remaining circuit board layers, the conductive patterns having conductive termination regions formed adjacent to the vertical edge portions. Conductive vertical vias are formed along vertical edge portions of a plurality of circuit board layers in electrical communication with the conductive termination regions. Flexible conductive strips are applied to the integrated circuit in electrical communication with the integrated circuit terminals.