Abstract: One embodiment of the present invention provides a system that performs both error-check and exact-check operations for a Newton-Raphson divide or square-root computation. During operation, the system performs Newton-Raphson iterations followed by a multiply for a divide or a square-root operation to produce a result, which includes one or more additional bits of accuracy beyond a desired accuracy for the result. Next, the system rounds the result to the desired accuracy to produce a rounded result t. The system then analyzes the additional bits of accuracy to determine whether t is correct and whether t is exact.

Abstract: One embodiment of the present invention provides a system that performs both error-check and exact-check operations for a Newton-Raphson divide or square-root computation. During operation, the system performs Newton-Raphson iterations followed by a multiply for a divide or a square-root operation to produce a result, which includes one or more additional bits of accuracy beyond a desired accuracy for the result. Next, the system rounds the result to the desired accuracy to produce a rounded result t. The system then analyzes the additional bits of accuracy to determine whether t is correct and whether t is exact.

Abstract: An interconnect device for transmitting data packets includes a plurality of ports, a hub, and an arbiter. The hub is configured to connect the plurality of ports together. The arbiter is coupled to the hub for controlling transmission of data packets between the hub and the ports. A reset is provided in at least one of the ports. The reset is in communication with the arbiter such that arbiter can reset the port in response to a detected error in the port.

Abstract: A method and system for maintaining TBS consistency between a flow control unit and central arbiter associated with an interconnect device in a communications network. In one embodiment, a method comprises synchronizing an available credit value between an arbiter and a first flow control unit, wherein the arbiter and flow control unit are part of a first interconnect device. An outgoing flow control message associated with the available credit value is sent; wherein the flow control message prevents packet loss and underutilization of the interconnect device.

Abstract: A pipelined floating point multiplier is disclosed having the capability of interleaving floating point multiplication with iterative floating point operations (calculations), such as division and square-root taking, by making use of idle stages (pipeline bubbles). This is accomplished with minimal additional circuitry over that required for conventional floating-point multipliers, and does not adversely affect the speed of iterative calculations. Method and apparatus are disclosed.