Abstract: A system and method are provided for displaying input signals from a DUT on a display screen. The method includes sending a data stream of digitized data received from the DUT to an FPGA for serial decoding; receiving decoded symbols from the FPGA; identifying valid symbols among the decoded symbols indicating transitions between the decoded symbols; storing the valid symbols with corresponding time-tags as valid packets in memory, and discarding ones of the decoded symbols occurring between the valid symbols; and plotting on the display screen the valid packets occurring between beginning and ending valid packets of the stored valid packets. The beginning valid packet has a corresponding time-tag occurring immediately before a first point time-tag associated with a left edge of the display screen, and the ending valid packet has a corresponding time-tag occurring at or immediately before a last point time-tag associated with a right edge of the display screen.

Abstract: A measurement system is provided that has a digital edge trigger circuit that is capable of operating at the full signal bandwidth of the measurement system. The digital edge trigger circuit comprises a plurality of processors that process time-interleaved digital data samples output from respective time-interleaved ADCs to perform edge trigger detection. The processors share edge detection information with one another to increase the speed at which edge trigger detection is performed to enable the digital edge trigger circuit to operate at the full signal bandwidth of the measurement system.

Abstract: A measurement system is provided that performs a trigger data acquisition algorithm. When the measurement system performs the trigger event data acquisition algorithm, it causes a preselected number of digital data samples acquired during a first time window that includes a trigger event and during a second time window that is specified by the user and that is subsequent in time to the first time window to be stored in memory. Digital data samples acquired after the end of the first time window and before the beginning of the second time window are not stored in memory. By not storing digital data samples acquired after the end of the first time window and before the beginning of the second time window, the possibility of overwriting samples that surround the trigger event is prevented and the memory is used very efficiently.

Abstract: A measurement system is provided that performs a qualified store algorithm. When performing the algorithm, the measurement system stores in memory digital data samples acquired during a time window while a qualification signal is valid, a preselected number of digital data samples acquired prior to and adjacent in time to the time window, and a preselected number of digital data samples acquired subsequent to and adjacent in time to the time window.

Abstract: A measurement system is provided that has a digital edge trigger circuit that is capable of operating at the full signal bandwidth of the measurement system. The digital edge trigger circuit comprises a plurality of processors that process time-interleaved digital data samples output from respective time-interleaved ADCs to perform edge trigger detection. The processors share edge detection information with one another to increase the speed at which edge trigger detection is performed to enable the digital edge trigger circuit to operate at the full signal bandwidth of the measurement system.

Abstract: A measurement system is provided that performs a qualified store algorithm. When performing the algorithm, the measurement system stores in memory digital data samples acquired during a time window while a qualification signal is valid, a preselected number of digital data samples acquired prior to and adjacent in time to the time window, and a preselected number of digital data samples acquired subsequent to and adjacent in time to the time window.

Abstract: A measurement system is provided that performs a trigger data acquisition algorithm. When the measurement system performs the trigger event data acquisition algorithm, it causes a preselected number of digital data samples acquired during a first time window that includes a trigger event and during a second time window that is specified by the user and that is subsequent in time to the first time window to be stored in memory. Digital data samples acquired after the end of the first time window and before the beginning of the second time window are not stored in memory. By not storing digital data samples acquired after the end of the first time window and before the beginning of the second time window, the possibility of overwriting samples that surround the trigger event is prevented and the memory is used very efficiently.

Abstract: An apparatus and method for determining if ringing in an output signal from a receiver that processes an input signal is the result of a bandwidth limitation in the receiver that processes an input signal rather than ringing in the input signal is disclosed. The apparatus includes the receiver and a ring suppression filter. The ring suppression filter receives the receiver output signal and generates a ring suppressed output signal therefrom. The receiver and the ring suppression filter provide a first aggregate system response such that the ring suppressed output signal does not include ringing introduced by the receiver. The first aggregate system response is linear in phase.

Abstract: An apparatus and method for determining if ringing in an output signal from a receiver that processes an input signal is the result of a bandwidth limitation in the receiver that processes an input signal rather than ringing in the input signal is disclosed. The apparatus includes the receiver and a ring suppression filter. The ring suppression filter receives the receiver output signal and generates a ring suppressed output signal therefrom. The receiver and the ring suppression filter provide a first aggregate system response such that the ring suppressed output signal does not include ringing introduced by the receiver. The first aggregate system response is linear in phase.

Abstract: Equalized Acquisition Record are prepared from Original Acquisition Records reflecting Total Jitter and from an existing description of DDJ. Removal of timing DDJ alters the locations of edges associated with data events. Voltage DDJ adjusts the asserted voltage in the central portion of a Unit Interval. One technique for equalizing timing jitter variably interpolates along the existing Original Acquisition Record to discover plausible new voltage values to assign to existing sample locations along the time axis. Another technique construes the desired amount of correction for each data event as an impulse that is applied to a Finite Impulse Response Filter whose output is a Voltage Correction Waveform having a smoothed voltage excursion. Time variant voltage values output from the Finite Impulse Response Filter are collected into a Voltage Correction Waveform Record having entry times found in the Original Acquisition Record.

Abstract: Separation and analysis of measured Total Jitter (TJ) begins with a suitably long arbitrary digital test pattern, from which an Acquisition Record is made. A Time Interval Error (TIE) or Voltage Level Error (VLE) Record is made of the Acquisition Record. A Template defines a collection of associated bit value or transitions that are nearby or otherwise related to a bit location of interest, and has associated therewith a collection of Descriptors and their respective Metrics. Each Descriptor identifies one of the various different patterns of bit value or transitions that fit the Template. The TIE/VLE Record is examined, and a parameter is measured for each instance of each Descriptor for the Template. The collection of measured parameters for each particular Descriptor are combined (e.g., averaging) to produce the Metric for that Descriptor.

Abstract: Measurement of jitter in a system uses a digital test sequence including many repetitions of a test pattern. An Acquisition Record is made of the entire test sequence. A complete Time Interval Error (TIE) Record is made of the Acquisition Record. The complete TIE Record is separated into a collection of Component TIE Records, one for each transition in the test pattern, and that collectively contain all the different instances in the test sequence of that transition in the test pattern. An FFT is performed on each component TIE Record, and the component FFTs are processed to obtain timing jitter data for the digital signal.

Abstract: Discovery of RJ assumes an Adjusted TIE Record for TJ from which DDJ has been removed. What remains is PJ+RJ, from whose Fourier Transform PJ is ‘synthetically de-convolved’ to leave just RJ: Calculate the Power Density Spectrum of PJ+RJ, and determine a threshold that indicates a PJ component. Identify in the PDS the largest frequency component that exceeds the threshold, otherwise there is no significant PJ and PJ+RJ can be taken as RJ. If a frequency component exceeds the threshold, take the largest and calculate what the convolution of it with the FT of the Transition Pattern would be if this circumstance were to occur in isolation, and then remove it from PJ+RJ. Repeat with continued iterations, until there are no further PJ components.

Abstract: Discovery of DDJ within measured Total Jitter (TJ) begins with a suitably long digital Test Pattern, from which an Acquisition Record is made. A Time Interval Error/Voltage Error Record is made of the Acquisition Record. A Template defines a collection of associated bit value or transitions that are nearby or otherwise related to a bit location of interest, and through the applied test pattern produces a sequence of Data Symbols. The TIE/VLE Record is examined, and a parameter is measured for each Data Symbol as it occurs in the Test Pattern. A regression technique may be use to find coefficients for a DDJ Calculator whose inputs are the Data Symbols and whose output is respective values of DDJ. Subsequent separation of DDJ from TJ is possible because DDJ is correlated with the Data Symbols, while Periodic Jitter (PJ) and Random Jitter (RJ) can be expected to average to near zero over a sufficient number of instances of a given Data Symbol.

Abstract: An I/O interface provides multiple serial data lines each with an embedded clock to provide sufficient data handling capacity to accommodate high data rates that are associated with high-speed data converters.

Abstract: A method of data acquisition for a digital instrument having a bandwidth. The method includes receiving a signal and associated trigger. Using that trigger, a plurality of signal values is sampled at multiple time intervals to create an acquisition record representing a continuous fractional segment of the signal. The plurality of samples meets the Nyquist requirement for the bandwidth but is in error according to at least one known error mechanism. The acquisition record is then processed with DSP techniques to produce a compensated acquisition record corrected for the at least one known error mechanism. Each associated compensated acquisition record is incorporated into a result acquisition record as a segment thereof corresponding to a continuous fractional segment of the signal whose signal values were sampled in an associated instance. An additional signal and additional associated trigger are received. The above steps are then repeated for the additional signal and additional associated trigger.

Abstract: Equalized Acquisition Record are prepared from Original Acquisition Records reflecting Total Jitter and from an existing description of DDJ. Removal of timing DDJ alters the locations of edges associated with data events. Voltage DDJ adjusts the asserted voltage in the central portion of a Unit Interval. One technique for equalizing timing jitter variably interpolates along the existing Original Acquisition Record to discover plausible new voltage values to assign to existing sample locations along the time axis. Another technique construes the desired amount of correction for each data event as an impulse that is applied to a Finite Impulse Response Filter whose output is a Voltage Correction Waveform having a smoothed voltage excursion. Time variant voltage values output from the Finite Impulse Response Filter are collected into a Voltage Correction Waveform Record having entry times found in the Original Acquisition Record.

Abstract: Separation and analysis of measured Total Jitter (TJ) begins with a suitably long arbitrary digital test pattern, from which an Acquisition Record is made. A Time Interval Error (TIE) or Voltage Level Error (VLE) Record is made of the Acquisition Record. A Template defines a collection of associated bit value or transitions that are nearby or otherwise related to a bit location of interest, and has associated therewith a collection of Descriptors and their respective Metrics. Each Descriptor identifies one of the various different patterns of bit value or transitions that fit the Template. The TIE/VLE Record is examined, and a parameter is measured for each instance of each Descriptor for the Template. The collection of measured parameters for each particular Descriptor are combined (e.g., averaging) to produce the Metric for that Descriptor.

Abstract: Measurement of jitter in a system uses a digital test sequence comprising many repetitions of a test pattern. An Acquisition Record is made of the entire test sequence. A complete Time Interval Error Record is made of the Acquisition Record. The complete TIE Record is separated into a collection of Component TIE Records, one for each transition in the test pattern, and that collectively contain all the different instances in the test sequence of that transition in the test pattern. An FFT is performed on each component TIE Record, and the collected DC contributions of those FFTs are combined to produce indications of Data Dependent Jitter, both as a function of bit position within the test pattern, and for the test sequence as a whole. The various spectral content of the FFTs for the component TIE Records are combined to produce an indication of Random Jitter and Periodic Jitter, which can then be used in finding Deterministic Jitter and Total Jitter.

Abstract: A method of data acquisition for a digital instrument having a bandwidth. The method includes receiving a signal and associated trigger. Using that trigger, a plurality of signal values is sampled at multiple time intervals to create an acquisition record representing a continuous fractional segment of the signal. The plurality of samples meets the Nyquist requirement for the bandwidth but is in error according to at least one known error mechanism. The acquisition record is then processed with DSP techniques to produce a compensated acquisition record corrected for the at least one known error mechanism. Each associated compensated acquisition record is incorporated into a result acquisition record as a segment thereof corresponding to a continuous fractional segment of the signal whose signal values were sampled in an associated instance. An additional signal and additional associated trigger are received. The above steps are then repeated for the additional signal and additional associated trigger.