Abstract: A system for controlling a clock rate of a microprocessor which includes a core clock operatively coupled to the processor, the core clock providing the microprocessor with a core clock signal for clocking the processor. A power supply operatively coupled to the microprocessor provides power to the processor. An intelligent clock generating system provides the core clock with at least one clock signal of a plurality of clock signals to be used as the core clock signal, wherein the plurality of clock signals includes a master clock signal and at least one ramped clock signal.

Abstract: Exchangeable LID modules are provided to enable the frame relay switching system to be interfaced to a specific data terminal, for example, synchronous, asynchronous terminals or T1 line, by performing on the receive side the physical translation of information on the input lines to clock signal CLK and HDLC framed data. On the transmit side, the HDLC framed data and clock signal CLK are translated into the data appropriate for a data terminal. The type of the translation is specific to the line to be interfaced with. To support a synchronous data terminal, a synchronous receiver is provided that extracts valid data patterns from a synchronous data stream. The data patterns are replaced with the data stream of appropriate levels when data are transmitted. When data are received from a T1 line, the LID splits the received data stream into user data and signalling data.

Abstract: In a fast-packet network, incoming high-level data-link control (HDLC) data are supplied by a receiving line interface device to a packet management device comprising a receiving state machine that shifts the data through a data link connection identifier (DLCI) extractor. The extracted DLCI is used as an address indicating a location of a translation RAM that stores the destination DLCI and control data corresponding to the incoming HDLC data. The destination DLCI replaces the current DLCI field of the incoming data. A frame control state machine requests a frame buffer of a frame buffer RAM to be allocated to the incoming HDLC packet and writes the data to the allocated buffer. Simultaneously, a packet availability message is sent to the destination packet management device indicated by the control data in the translation RAM. A transmitting circuit of the destination packet management device has a transmitting state machine that rewrites the HDLC data from the frame buffer RAM to a FIFO register.

Abstract: A modular architecture for fast-packet networks that comprises line interface devices (LIDs) exchangeable to support numerous line interfaces. The LIDs supply frame relay packet management devices (FRYPAMs) with unified framed data in high-level data-link control (HDLC) format and clock signals. The receiving FRYPAMs perform cyclic redundancy check (CRC) checking, check look-up tables to convert the data link connection identifier (DLCI) fields if needed, write the received frames with correct frame check sequence (FCS) fields into a frame buffer RAM and communicate with other FRYPAMs to update transmission queues. The transmitting FRYPAMs read the frames from the frame buffer RAM and send them to the transmitting LIDs coupled to destination end points. The transmitting LIDs convert the HDLC data from the FRYPAMs to the format appropriate for the specific line interface and transmit the information to the destination end points.