Abstract: A method and processor to evaluate a monotonicity of a set of input values is disclosed. The processor achieves high processing power by means of an arbitrary number of identical parallel processing elements. Each processing element allows instruction dependent data paths and makes use of ALU factories which consist of a number of separate arithmetic logical units (ALUs) are arranged in a special kind of matrix. The processor allows parallel evaluation and analysis of the monotonicity of a multitude of sets of values. A threshold value can be freely configured to allow an uncertainty of nearly equal values which is of high importance in digital signal processing.

Abstract: A method and apparatus to control execution of nested loops is disclosed. The method and apparatus stores the loop level of a current loop in execution and uses this loop level to manage a data set provided for each loop. The data set for each loop includes a start address, an end address, and a loop counter or a loop flag, respectively. The method and apparatus allows arbitrary nested loops to be controlled without increasing a complexity level of the circuit and allows additional loop control. The only precondition is that the loop end addresses are different.

Abstract: In some embodiments a flexible scalable Boolean processing apparatus is disclosed. The apparatus can include a register to accept Boolean inputs, a Boolean lookup table coupled to the register to accept the Boolean inputs and to perform a Boolean function on the Boolean inputs and to produce a result. The apparatus can also include a multiplexer to select an executable instruction to process the result in response to an instruction select signal. In some embodiments the apparatus can include a shifter module to shift the result to a predetermined bit location in a register and a filler module to fill the register if a result has fewer bits than a number of bits required to fill the register. Other embodiments are also disclosed.

Abstract: Methods and apparatuses that can determining a median value from a set of m values are disclosed. The method can include receiving a set of values, separating the set of values into subsets where some subsets have multiple values and at least one other has a single value. The subsets having multiple variables can be sorted based on the magnitudes of the multiple values. The values from the subset can be processed to find sub-median values, and a median value can be determined from the set of values utilizing the sub-median values and sorted values. Other embodiments are also disclosed.

Abstract: The invention relates to a digital signal processing device comprising: input storage means (3; 5); a computational device (4) that is connected to said means, defines a data path (9) and contains at least one arithmetic unit (6) in addition to a control input (2a) for specifying calculation operations; and output storage means (8). The data path (9) between the arithmetic unit (6; 7) and the output storage means (8) is equipped with a number-format conversion unit (10) comprising a shift unit (17). A number-format specification unit (11) and a control unit (17), which is connected to the latter and calculates required shift operations on the basis of the number-format specification, are assigned to the number-format conversion unit (10). Formatting operations are calculated automatically using input and output format information and corresponding commands are applied to the shift unit (17).

Abstract: A process for controlling the preconduction current of a laser diode that operates in conjunction with a monitor diode in a control circuit with operational amplifiers, comprising signal processing filters, an electric supply unit such as, e.g., a power source, and a zero crossing detector, where the laser diode (5a) is driven by a linear current ramp signal provided by the supply unit, that the output signal (16) of the monitor diode (15) is differentiated three times, and that, when a zero crossing of the triple-differentiated monitor diode output signal (16) is detected, an optimum current of the current ramp signal is retained by the action of the zero passage detector.