Abstract: Disclosed is a flip-flop (FF) (e.g., a D-type flip-flop (DFF) or a scan flip-flop (SFF)). The FF is configured to reduce dynamic power consumption of an integrated circuit (IC) by employing only a single-phase of a clock signal. Specifically, the FF includes a primary latch and a secondary latch. Each of these latches includes a multi-stage input driver, which internally generates a control signal based on both the single-phase clock signal and an input signal and which also generates a stored bit signal based on the control signal. Each of these latches can also include a feedback path with an inverter that inverts the stored bit signal and a tri-state logic device that generates a feedback signal that is dependent on the inverted stored bit signal, the control signal and the clock signal. As a result, the FF is a fully digital, static, true single-phase clock (TSPC) flip-flop.

Abstract: Generally described, one or more aspects of the present application correspond to a machine learning address normalization system. A system of deep learning networks can normalize the tokens of a free-form address into an address component hierarchy. Feature vectors representing various characters and words of the address tokens can be input into a bi-directional long short term memory network (LSTM) to generate a hidden state representation of each token, which can be individually passed through a softmax layer to generate probabilistic values of the token being each of the components in the address hierarchy. Thereafter, a conditional random field (CRF) model can select a particular address component for each token by using learned parameters to optimize a path through the collective outputs of the softmax layer for the tokens. Thus, the free-form address can be normalized to determine the values it contains for different components of a specified address hierarchy.

Abstract: Disclosed are scan flip-flops (SFFs) that reduce the dynamic power consumption of a system-on-chip (SOC) that incorporates them. Each SFF includes a master latch and a slave latch, each having a driver, a feed-forward path and a feedback path. Each SFF further includes at least one shared clock-gated power supply transistor, which is controlled by either a clock signal or an inverted clock signal to selectively and simultaneously connect a voltage rail to both the driver from one latch and the feedback path of the other latch. The different SFF embodiments have different numbers of shared clock-gated power supply transistors and various other different features designed for optimal power and/or performance. For example, the different SFF embodiments have different types of slave latch drivers; different types of transistors; and/or different types of master latch drivers (e.g., a single-stage, multiple clock phase-dependent driver or a multi-stage, single clock phase-dependent driver).

Abstract: Disclosed are scan flip-flops (SFFs) that reduce the dynamic power consumption of a system-on-chip (SOC) that incorporates them. Each SFF includes a master latch and a slave latch, each having a driver, a feed-forward path and a feedback path. Each SFF further includes at least one shared clock-gated power supply transistor, which is controlled by either a clock signal or an inverted clock signal to selectively and simultaneously connect a voltage rail to both the driver from one latch and the feedback path of the other latch. The different SFF embodiments have different numbers of shared clock-gated power supply transistors and various other different features designed for optimal power and/or performance. For example, the different SFF embodiments have different types of slave latch drivers; different types of transistors; and/or different types of master latch drivers (e.g., a single-stage, multiple clock phase-dependent driver or a multi-stage, single clock phase-dependent driver).

Abstract: Systems and methods for reducing hot spots and recovering Vt/area to improve chip performance in an integrated circuit design. According to the method, physical grid areas for an IC chip are defined and a switching window for library elements of an integrated circuit design in a region of the chip is determined. Points of peak current for library elements within the switching window are determined. A grid area is selected and library elements having additional usable timing margin are identified. The library elements are prioritized, based on location in the grid area according to peak current and usable timing margin. Based on order of priority, the timing of signal paths in the grid area may be adjusted in order to misalign points of peak current and maintain current density in the region below a threshold and/or a library element within the grid area may be changed to recover area within the grid area.

Abstract: Disclosed are integrated circuit (IC) design methods, systems and computer program products that provide for area and/or power optimization through post-layout modification of design blocks. Specifically, a layout for an initial IC design is accessed. This initial IC design incorporates multiple instances of the same design block. Each instance includes a primary input connected to top-level logic for receiving a signal and one or more modifiable periphery sections. A timing analysis is performed to close timing and determine arrival times of the signal at the primary inputs of all instances of the design block, respectively, given the layout. The arrival times are then compared to a preselected threshold arrival time and the modifiable periphery section(s) of any specific instance of the design block having an arrival time that is equal to or less than the preselected threshold arrival time is selectively modified in order to generate an area and/or power optimized integrated circuit design.

Abstract: Disclosed are temperature-aware integrated circuit (IC) design methods and systems, which establish a customized power delivery network (PDN) for an IC early in the design process in order to generate, in a timely manner, a final IC design layout that can be used to manufacture IC chips that will exhibit minimal hotspots. Specifically, prior to placement of library elements, an initial PDN is established and divided into sections. The library elements are placed. Then, potential hotspots associated with any of the sections are identified and a customized PDN for the IC is established to eliminate the hotspots. That is, for each section, a total power consumption amount is determined. When the total power consumption amount is greater than the threshold, a hotspot is indicated and the section is customized to eliminate the hotspot. Also disclosed is a resulting IC chip structure.

Abstract: Disclosed are electromigration (EM)-aware integrated circuit (IC) design techniques, which consider EM early in the IC design process in order to generate, in a timely manner, an IC design that can be used to manufacture IC chips that will exhibit minimal EM fails for improved IC reliability. Specifically, prior to placement of library elements, EM-relevant information is acquired and used to define protected zones around at least some of the library elements. Once the protected zones are defined, the library elements are placed relative to power rails in a previously designed power delivery network (PDN) and this placement process is performed such that each library element is prevented from being placed in a protected zone around any other library element to avoid EM fails in the PDN. Optionally, this same EM-relevant information is used during subsequent synthesis of a clock distribution network to prevent EM fails therein.

Abstract: Disclosed are integrated circuit (IC) design methods, systems and computer program products that provide for area and/or power optimization through post-layout modification of design blocks. Specifically, a layout for an initial IC design is accessed. This initial IC design incorporates multiple instances of the same design block. Each instance includes a primary input connected to top-level logic for receiving a signal and one or more modifiable periphery sections. A timing analysis is performed to close timing and determine arrival times of the signal at the primary inputs of all instances of the design block, respectively, given the layout. The arrival times are then compared to a preselected threshold arrival time and the modifiable periphery section(s) of any specific instance of the design block having an arrival time that is equal to or less than the preselected threshold arrival time is selectively modified in order to generate an area and/or power optimized integrated circuit design.

Abstract: Disclosed are temperature-aware integrated circuit (IC) design methods and systems, which establish a customized power delivery network (PDN) for an IC early in the design process in order to generate, in a timely manner, a final IC design layout that can be used to manufacture IC chips that will exhibit minimal hotspots. Specifically, prior to placement of library elements, an initial PDN is established and divided into sections. The library elements are placed. Then, potential hotspots associated with any of the sections are identified and a customized PDN for the IC is established to eliminate the hotspots. That is, for each section, a total power consumption amount is determined. When the total power consumption amount is greater than the threshold, a hotspot is indicated and the section is customized to eliminate the hotspot. Also disclosed is a resulting IC chip structure.

Abstract: Disclosed are electromigration (EM)-aware integrated circuit (IC) design techniques, which consider EM early in the IC design process in order to generate, in a timely manner, an IC design that can be used to manufacture IC chips that will exhibit minimal EM fails for improved IC reliability. Specifically, prior to placement of library elements, EM-relevant information is acquired and used to define protected zones around at least some of the library elements. Once the protected zones are defined, the library elements are placed relative to power rails in a previously designed power delivery network (PDN) and this placement process is performed such that each library element is prevented from being placed in a protected zone around any other library element to avoid EM fails in the PDN. Optionally, this same EM-relevant information is used during subsequent synthesis of a clock distribution network to prevent EM fails therein.

Abstract: Disclosed is a method of making a bismuth molybdate precursor solution using a metallorganic decomposition (MOD) process consisting of the formation of a precursor sol of hexanoates of Bismuth (Bi) and Molybdenum (Mo). The precursor solution is used to make thin film of Bismuth molybdate by spin coating and spray pyrolysis. The bismuth molybdate films have the useful alpha and gamma phases having high sensitivity to ethanol gas, the detection of the ethanol gas is based upon the change of electrical conductivity of a thick film of the semiconductor oxide sensing element resulting from the ethanol gas in an oxygen-containing atmosphere. When the drying is effected by spray pyrolysis, quite thick films with high adhesion have been produced over different substrates, including quartz. The thin film of the present invention made by spray pyrolysis has a very fast response to ethanol detection eg typically 5 seconds.

Abstract: Disclosed is a method of making a bismuth molybdate precursor solution using a metallorganic decomposition (MOD) process consisting of the formation of a precursor sol of hexanoates of Bismuth (Bi) and Molybdenum (Mo). The precursor solution is used to make thin film of Bismuth molybdate by spin coating and spray pyrolysis. The bismuth molybdate films have the useful alpha and gamma phases having high sensitivity to ethanol gas, the detection of the ethanol gas is based upon the change of electrical conductivity of a thick film of the semiconductor oxide sensing element resulting from the ethanol gas in an oxygen-containing atmosphere. When the drying is effected by spray pyrolysis, quite thick films with high adhesion have been produced over different substrates, including quartz. The thin film of the present invention made by spray pyrolysis has a very fast response to ethanol detection eg typically 5 seconds.