Abstract: A video processing device is disclosed that includes a processor unit with a processor and a memory having a reorder buffer. The processor includes a reorder module, a frame rate conversion module, and post-processing function modules. The reorder, frame rate conversion, and post-processing modules access video frames stored in the reorder buffer, while the video frames are stored in the reorder buffer, and reorder, adjust the frame rate, and perform image processing, respectively, on the video frames, while the video frames are stored in the reorder buffer. A method implemented on such a video processing device is also disclosed. A computer-readable storage medium with instructions stored thereon for performing the method is also disclosed.