Abstract: A behavior detection module constructs a random forest classifier (RFC) that takes into account asymmetric misclassification costs between a set of classification labels. The classification label estimate is determined based on classification estimates from the plurality of decision trees. Each parent node of a decision tree is associated with a condition of an attribute that splits a parent node into two child nodes by maximizing an improvement function based on a training database. The improvement function is based on an asymmetric impurity function that biases the decision tree to decrease the error for a label with high misclassification cost over the other, at the cost of increasing the error of the other label with a lower misclassification cost.

Abstract: A behavior detection module constructs a random forest classifier (RFC) that takes into account asymmetric misclassification costs between a set of classification labels. The classification label estimate is determined based on classification estimates from the plurality of decision trees. Each parent node of a decision tree is associated with a condition of an attribute that splits a parent node into two child nodes by maximizing an improvement function based on a training database. The improvement function is based on an asymmetric impurity function that biases the decision tree to decrease the error for a label with high misclassification cost over the other, at the cost of increasing the error of the other label with a lower misclassification cost.

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

Abstract: A data storage device is presented that includes a plurality of storage drives each comprising an associated drive Peripheral Component Interconnect Express (PCIe) interface. The data storage device also includes a control system configured to receive, over a host PCIe link, write operations for storage of data by the data storage device. The control system is configured to process the write operations against storage allocation information to apportion the data for storage among more than one of the storage drives, and transfer corresponding portions of the data to associated storage drives over corresponding drive PCIe interfaces.

Abstract: A data storage device is presented that includes an interface system configured to communicate over an aggregated host link comprising Peripheral Component Interconnect Express (PCIe) interfaces to receive one or more write operations for storage of data by the data storage device. The data storage device includes plurality solid state drives (SSDs) each comprising drive PCIe interfaces coupled to the interface system. The interface system is configured to process the one or more write operations against storage allocation information to parallelize the data among the SSDs and transfer portions of the parallelized data to associated SSDs over corresponding drive PCIe interfaces.

Abstract: In some embodiments, a meta-data inspection data store may contain hierarchical components and subcomponents of an industrial asset and define points of interest. An industrial asset inspection platform may access that information and generate an inspection plan, including an association of at least one sensor type with each of the points of interest. The platform may then store information about the inspection plan in an inspection plan data store and receive inspection data (e.g., from a manual inspection, from an inspection robot, from a fixed sensor, etc.). A smart tagging algorithm may be executed to associate at least one point of interest with an appropriate portion of the received inspection data based on information in the inspection plan data store.

Abstract: A method for updating a DRAM memory array is disclosed. The method comprises: a) transitioning the DRAM memory array from an idle state to a refresh state in accordance with a command from a memory controller; b) initiating a refresh on the DRAM memory array using DRAM internal control circuitry by activating a row of data into an associated sense amplifier buffer; and c) during the refresh, performing an ERR Correction Code (ECC) scrub operation of selected bits in the activated row of the DRAM memory array.

Abstract: Computer-implemented methods for mapping sensor tags of assets to input ports of an analytic process are disclosed. In an embodiment, a processor receives a selection by a user of an analytic process to run on a plurality of assets, automatically maps the analytic input ports of the selected analytic process to sensor tags of each of the plurality of assets that have matching tag names, and determines which analytic input ports have not been fully mapped. The processor then provides a map by asset option and a map by tag option to the user device, receives a selection of the map by asset option, provides an unmapped assets list including at least one asset that is not fully mapped and a list of tag alias names, and then receives a selection from the user device of an asset from the unmapped assets list along with selections of tag alias names mapped to the unmapped analytic input ports of the selected analytic process.

Abstract: Techniques are disclosed relating to multi-factor authentication of a user. In one embodiment, a computing device presents a one-time password to a user that has a sequence of characters. In response to presenting the one-time password, in various embodiments, the computing device receives a first sequence of fingers supplied by the user to a fingerprint sensor of the computing device. In some embodiments, the computing device converts the one-time password to a second sequence of fingers based on a mapping that associates fingers with characters. In one embodiment, the computer system authenticates the user by comparing the first sequence of fingers with the second sequence of fingers. In various embodiments, these actions may be performed in the context of a client-server interaction.

Abstract: A method for updating a DRAM memory array is disclosed. The method comprises: a) transitioning the DRAM memory array from an idle state to a refresh state in accordance with a command from a memory controller; b) initiating a refresh on the DRAM memory array using DRAM internal control circuitry by activating a row of data into an associated sense amplifier buffer; and c) during the refresh, performing an ERR Correction Code (ECC) scrub operation of selected bits in the activated row of the DRAM memory array.

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

Abstract: One embodiment of the present invention sets forth a method for accessing non-contiguous locations within a DRAM memory page by sending a first column address command to a first DRAM device using a first subset of pins and sending a second column address command to a second DRAM device using a second subset of repurposed pins. The technique requires minimal additional pins, space, and power consumption. Further, sending multiple column address commands allows for increased granularity of DRAM accesses and therefore more efficient use of pins. The technique for accessing non-contiguous locations within a DRAM memory page.

Abstract: A method is described for storing a plurality of access tokens, each access token associated with a respective login credential of a plurality of login credentials, and each access token usable to access a respective account of a plurality of accounts of a user. The method further comprising receiving a transaction request from the user for a transaction with a target account and determining a respective user login status of the user for ones of the plurality of accounts using respective access tokens. The method further comprising determining which of at least two actions to take in response to determining whether the user login status of a predefined number of the plurality of accounts is active.

Abstract: Techniques are disclosed relating to authorization of asset sharing between user accounts. In some embodiments, a server-side method includes storing account information for a first user account and receiving a first request to share funds from the first user account with a second user account. In some embodiments, the first request includes one or more constraints on the shared funds. In some embodiments, the method further includes authenticating that the first request was received from a user authorized to share funds from the first user account, receiving a second request that is an authorization request for a payment transaction initiated by the second user account, and authorizing, in response to determining that the second request meets the one or more constraints, the second user account to access the shared funds for the payment transaction. In some embodiments, the shared funds are not transferred from the first user account until after receiving the second request.

Abstract: Disclosed are novel processes to increase productivity on a continuous anneal and solution heat treatment line for heat-treatable automotive aluminum sheet products with high T4 and after-paint bake strengths and reduced roping. As a non-limiting example, the processes described herein can be used in the automotive industry. The disclosed heat treatable alloys and processes also may be applicable to the marine, aerospace, and transportation industries.

Abstract: In one embodiment, a method for updating a DRAM memory array is disclosed. The method comprises: a) transitioning the DRAM memory array from an idle state to a self-refresh state after a period of inactivity; b) initiating a refresh on the DRAM memory array using DRAM internal control circuitry; and c) during the refresh, performing an Error Correction Code (ECC) scrub operation of selected bits in an activated row of the DRAM memory array.

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

Abstract: Disclosed are novel processes to increase productivity on a continuous anneal and solution heat treatment line for heat-treatable automotive aluminum sheet products with high T4 and after-paint bake strengths and reduced roping. As a non-limiting example, the processes described herein can be used in the automotive industry. The disclosed heat treatable alloys and processes also may be applicable to the marine, aerospace, and transportation industries.

Abstract: One embodiment sets forth a technique for time-multiplexed communication for transmitting command and address information between a controller and a multi-port memory device over a single connection. Command and address information for each port of the multi-port memory device is time-multiplexed within the controller to produce a single stream of commands and addresses for different memory requests. The single stream of commands and addresses is transmitted by the controller to the multi-port memory device where the single stream is demultiplexed to generate separate streams of commands and addresses for each port of the multi-port memory device.

Abstract: A method for updating a DRAM memory array is disclosed. The method comprises: a) receiving a command from a memory controller to initiate an active cycle for activating a memory row in a DRAM memory array; b) performing an Error Correction Code (ECC) scrub on the memory row prior to reading data from the memory row into sense amplifiers in the DRAM memory array in accordance with the command to activate; c) activating the memory row; and d) writing corrected data following the ECC scrub back into memory from the sense amplifiers during a pre-charge cycle of the DRAM memory array.