Patents by Inventor Alon Gluska
Alon Gluska has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9972062Abstract: Flood-fill techniques and architecture are disclosed. In accordance with one embodiment, the architecture comprises a hardware primitive with a software interface which collectively allow for both data-based and task-based parallelism in executing a flood-fill process. The hardware primitive is defined to do the flood-fill function and is scalable and may be implemented with a bitwise definition that can be tuned to meet power/performance targets, in some embodiments. In executing a flood-fill operation, and in accordance with an example embodiment, the software interface produces parallel threads and issues them to processing elements, such that each of the threads can run independently until done. Each processing element in turn accesses a flood-fill hardware primitive, each of which is configured to flood a seed inside an N×M image block. In some cases, processing element commands to the flood-fill hardware primitive(s) can be queued and acted upon pursuant to an arbitration scheme.Type: GrantFiled: November 21, 2014Date of Patent: May 15, 2018Assignee: INTEL CORPORATIONInventors: Alon Gluska, Niraj Gupta, Mostafa Hagog, Dror Reif
-
Publication number: 20150077422Abstract: Flood-fill techniques and architecture are disclosed. In accordance with one embodiment, the architecture comprises a hardware primitive with a software interface which collectively allow for both data-based and task-based parallelism in executing a flood-fill process. The hardware primitive is defined to do the flood-fill function and is scalable and may be implemented with a bitwise definition that can be tuned to meet power/performance targets, in some embodiments. In executing a flood-fill operation, and in accordance with an example embodiment, the software interface produces parallel threads and issues them to processing elements, such that each of the threads can run independently until done. Each processing element in turn accesses a flood-fill hardware primitive, each of which is configured to flood a seed inside an N×M image block. In some cases, processing element commands to the flood-fill hardware primitive(s) can be queued and acted upon pursuant to an arbitration scheme.Type: ApplicationFiled: November 21, 2014Publication date: March 19, 2015Applicant: INTEL CORPORATIONInventors: Alon Gluska, Niraj Gupta, Mostafa Hagog, Dror Reif
-
Patent number: 8902238Abstract: Flood-fill techniques and architecture are disclosed. In accordance with one embodiment, the architecture comprises a hardware primitive with a software interface which collectively allow for both data-based and task-based parallelism in executing a flood-fill process. The hardware primitive is defined to do the flood-fill function and is scalable and may be implemented with a bitwise definition that can be tuned to meet power/performance targets, in some embodiments. In executing a flood-fill operation, and in accordance with an example embodiment, the software interface produces parallel threads and issues them to processing elements, such that each of the threads can run independently until done. Each processing element in turn accesses a flood-fill hardware primitive, each of which is configured to flood a seed inside an N×M image block. In some cases, processing element commands to the flood-fill hardware primitive(s) can be queued and acted upon pursuant to an arbitration scheme.Type: GrantFiled: October 15, 2012Date of Patent: December 2, 2014Assignee: Intel CorporationInventors: Alon Gluska, Niraj Gupta, Mostafa Hagog, Dror Reif
-
Publication number: 20140104285Abstract: Flood-fill techniques and architecture are disclosed. In accordance with one embodiment, the architecture comprises a hardware primitive with a software interface which collectively allow for both data-based and task-based parallelism in executing a flood-fill process. The hardware primitive is defined to do the flood-fill function and is scalable and may be implemented with a bitwise definition that can be tuned to meet power/performance targets, in some embodiments. In executing a flood-fill operation, and in accordance with an example embodiment, the software interface produces parallel threads and issues them to processing elements, such that each of the threads can run independently until done. Each processing element in turn accesses a flood-fill hardware primitive, each of which is configured to flood a seed inside an N×M image block. In some cases, processing element commands to the flood-fill hardware primitive(s) can be queued and acted upon pursuant to an arbitration scheme.Type: ApplicationFiled: October 15, 2012Publication date: April 17, 2014Inventors: Alon Gluska, Niraj Gupta, Mostafa Hagog, Dror Reif
-
Patent number: 6356858Abstract: Coverage measurement tool enabling a user to create a specific coverage tool for a coverage model including a set of coverage tasks specified by the user for checking a design such as a hardware or software system, and being associated with a database and model definition that defines the coverage model. The tool includes an insertion engine for storing into the database a table containing traces resulting from multiple tests, a processing engine processing the traces in the database according to the model definition, and a coverage analyzer analyzing the measurement results from the processing engine and preparing coverage analysis reports according to the model definition.Type: GrantFiled: February 12, 1999Date of Patent: March 12, 2002Assignee: International Business Machines Corp.Inventors: Yossi Malka, Alon Gluska, Schmuel Ur, Avi Ziv
-
Method for measuring architectural test coverage for design verification and building conformal test
Patent number: 5724504Abstract: A technique that applies the task coverage exercised within a behavioral model of the design to the design itself, while simulating one or more test sequences. Since the behavior model is an accurate and complete program representation of the architectural specification of the hardware design, the test case coverage of the architecture is implied by the measurement of how well the behavioral model code has been exercised. The completeness of the coverage is determined by the test coverage criteria selected, including, for example, statement coverage, branch coverage, or path coverage. The more detailed the criteria, the greater the number of tests.Type: GrantFiled: June 1, 1995Date of Patent: March 3, 1998Assignee: International Business Machines CorporationInventors: Aharon Aharon, Laurent Fournier, Alon Gluska, Yossi Lichtenstein, Yossi Malka -
Patent number: 5592674Abstract: A method for the automatic verification of external interrupts in modern processor architectures under a very wide range of instruction sequences provides almost complete expected results from each of the involved interrupts. In particular, the method allows the verification of the architectural aspects to the external interrupt mechanism in pipelined and super scalar microprocessors. The method which is based on the assumption that when an external interrupt is serviced, the processor branches to a specific address according to the type of the external interrupt. The first step in the method is a preparation step wherein the memory addresses already used by the test are scanned and unused memory spaces are allocated for a plurality of memory blocks and two memory addresses for pointers. These two addresses are used to find the next block to fill. After this initial preparation step, the interrupt is presented in any desired location by the design simulator controller.Type: GrantFiled: December 20, 1994Date of Patent: January 7, 1997Assignee: International Business Machines CorporationInventors: Alon Gluska, Laurent Fournier, Raanan Gewirtzman, Reuven Nisser
-
Patent number: 5542007Abstract: An improved method is disclosed of compressing, for storage or transmission, the information contained in a bi-level digitized input image by separate handling of a corresponding template image and a compressed image, which method is capable of handling "white-out" areas of the image. In accordance with the method, the template image is subtracted from the input image to generate the compressed image, the subtraction is characterized in that the subtraction step determines, for each pixel, whether the pixel is a "removed pixel" and, if so, the pixel is assigned to be black in the compressed image. A pixel is a "removed pixel" if the corresponding pixel in the template image is black, and the corresponding pixel in the input image is white.Type: GrantFiled: October 27, 1993Date of Patent: July 30, 1996Assignee: International Business Machines CorporationInventors: Dan Chevion, Alon Gluska, Ittai Gilat