Abstract: A single loop hardware-based system for producing laser pulses in a microsecond scale operational mode includes a GUI to enable a user to select the operational mode of the system; a laser source for producing one or more laser beam pulses, the laser source being a diode laser pump source module; a DSP which enables and disables a hardware-based FPGA. The FPGA controls the diode pump source module. When a user selects one or more microsecond scale laser sub-pulses on the GUI, the DSP transmits to the FPGA the sub-pulse energy level and the sub-pulse on-time selected by the user on the GUI. A photodetector operatively connected to the hardware-based system measures the power of the laser pulse beam that was transmitted to the photodetector and, in a feedback mode, transmits a feedback signal of that power measurement to the FPGA. The FPGA compares the power of the laser beam measured by the photodetector to the power of the laser beam selected by the user on the GUI.

Abstract: A device for insertion into a body lumen includes an operator unit which may be hand held by an operator. A cannula is operatively associated with the operator unit and the cannula includes two parallel lumens. At least one of two lumens terminates at its distal end before the distal end of the other lumen and wherein one of the two lumens is contained at most partially within the other lumen.

Abstract: A single loop hardware-based system for producing laser pulses in a microsecond scale operational mode includes a GUI to enable a user to select the operational mode of the system; a laser source for producing one or more laser beam pulses, the laser source being a diode laser pump source module; a DSP which enables and disables a hardware-based FPGA. The FPGA controls the diode pump source module. When a user selects one or more microsecond scale laser sub-pulses on the GUI, the DSP transmits to the FPGA the sub-pulse energy level and the sub-pulse on-time selected by the user on the GUI. A photodetector operatively connected to the hardware-based system measures the power of the laser pulse beam that was transmitted to the photodetector and, in a feedback mode, transmits a feedback signal of that power measurement to the FPGA. The FPGA compares the power of the laser beam measured by the photodetector to the power of the laser beam selected by the user on the GUI.

Abstract: A method of treating ophthalmic tissues of the body by the application of multiple laser pulses on each single spot intended to be treated while reducing heating of the ophthalmic tissues includes providing a source of pulsed laser energy movable in X and Y dimensions; determining the location and dimensions of the area of the ophthalmic tissue to be treated; determining an array of X rows by Y columns target spot positions within the area to be treated; then firing a single pulse of the source of laser energy at an initial target spot in the first of the X rows; firing a single second spot of laser energy at the next adjacent target spot along the first of the X rows and repeating the sequence until treatment is completed. A continuous wave (CW) laser energy source may also be utilized in practicing the method by moving the CW laser energy source in a determined pattern.

Abstract: A device for insertion into a body lumen includes an operator unit which may be hand held by an operator. A cannula is operatively associated with the operator unit and the cannula includes two parallel lumens. At least one of two lumens terminates at its distal end before the distal end of the other lumen and wherein one of the two lumens is contained at most partially within the other lumen.

Abstract: A single loop hardware-based system for producing laser pulses in a microsecond scale operational mode includes a GUI to enable a user to select the operational mode of the system; a laser source for producing one or more laser beam pulses, the laser source being a diode laser pump source module; a DSP which enables and disables a hardware-based FPGA. The FPGA controls the diode pump source module. When a user selects one or more microsecond scale laser sub-pulses on the GUI, the DSP transmits to the FPGA the sub-pulse energy level and the sub-pulse on-time selected by the user on the GUI. A photodetector operatively connected to the hardware-based system measures the power of the laser pulse beam that was transmitted to the photodetector and, in a feedback mode, transmits a feedback signal of that power measurement to the FPGA. The FPGA compares the power of the laser beam measured by the photodetector to the power of the laser beam selected by the user on the GUI.

Abstract: A device for insertion into a body lumen includes an operator unit which may be hand held by an operator. A cannula is operatively associated with the operator unit and the cannula includes two parallel lumens. At least one of two lumens terminates at its distal end before the distal end of the other lumen and wherein one of the two lumens is contained at most partially within the other lumen.

Abstract: A testability architecture and method for loosely integrated (modularized) integrated circuits uses stand alone module testing. For an integrated circuit chip which has a number of independent modules, where one module design is used in a number of different chips, each module is connected to the chip's input/output pins and to a configuration module. To make testing of the modules more efficient and less expensive, during testing of the chip a particular module design is confronted with the same testing environment regardless of the actual chip in which it is present. Advantageously, chip area is only slightly enlarged by the test circuitry. A test architecture of the configuration module includes test registers and carries out a standard protocol for all read and write transactions during testing. This approach provides better test coverage and economizes in test generation.

Abstract: A testability architecture and method for loosely integrated (modularized) integrated circuits uses stand alone module testing. For an integrated circuit chip which has a number of independent modules, where one module design is used in a number of different chips, each module is connected to the chip's input/output pins and to a configuration module. To make testing of the modules more efficient and less expensive, during testing of the chip a particular module design is confronted with the same testing environment regardless of the actual chip in which it is present. Advantageously, chip area is only slightly enlarged by the test circuitry. A test architecture of the configuration module includes test registers and carries out a standard protocol for all read and write transactions during testing. This approach provides better test coverage and economizes in test generation.

Abstract: The data separator of this invention may be used for extracting clock and data signals from a serial stream of bits read from a magnetic disk or tape. The data separator is supplied with a "fast" clock pulse generated by a frequency multiplexer. After a lock indication from the frequency multiplier, during the first eight serial data pulses the frequency and phase of the data separator are synchronized to the serial data pulses. Then an early and late logic unit keeps track digitally of the cumulative phase difference between the incoming data stream and the output of the data separator. When the cumulative phase difference reaches predetermined limits, the phase of the output is adjusted. If a second phase adjustment is required in the same direction (i.e., early or late), the frequency of the output is adjusted.

Abstract: The data separator of this invention may be used for extracting clock and data signals from a serial stream of bits read from a magnetic disk or tape. The data separator is supplied with a "fast" clock pulse generated by a frequency multiplexer. After a lock indication from the frequency multiplier, during the first eight serial data pulses the frequency and phase of the data separator are synchronized to the serial data pulses. Then an early and late logic unit keeps track digitally of the cumulative phase difference between the incoming data stream and the output of the data separator. When the cumulative phase difference reaches predetermined limits, the phase of the output is adjusted. If a second phase adjustment is required in the same direction (i.e., early or late), the frequency of the output is adjusted.

Abstract: A microprocessor architecture that includes capabilities for locking individual entries into its integrated instruction cache and data cache while leaving the remainder of the cache unlocked and available for use in capturing the microprocessor's dynamic locality of reference. The microprocessor also includes the capability for locking instruction cache entries without requiring that the instructions be executed during the locking process.