Abstract: A mixed-signal in-memory computing sub-cell only requires 9 transistors for 1-bit multiplication. A computing cell is constructed from a plurality of such sub-cells that share a common computing capacitor and a common transistor. A MAC array for performing MAC operations, includes a plurality of the computing cells each activating the sub-cells therein in a time-multiplexed manner. A differential version of the MAC array provides improved computation error tolerance and an in-memory mixed-signal computing module for digitalizing parallel analog outputs of the MAC array and for performing other tasks in the digital domain. An ADC block in the computing module makes full use of capacitors in the MAC array, allowing the computing module to have a reduced area and suffer from fewer computational errors.

Abstract: A mixed-signal in-memory computing sub-cell only requires 9 transistors for 1-bit multiplication. A computing cell is constructed from a plurality of such sub-cells that share a common computing capacitor and a common transistor. Also proposed is a MAC array for performing MAC operations, which includes a plurality of the computing cells each activating the sub-cells therein in a time-multiplexed manner. Also proposed is a differential version of the MAC array with improved computation error tolerance and an in-memory mixed-signal computing module for digitalizing parallel analog outputs of the MAC array and for performing other tasks in the digital domain. An ADC block in the computing module makes full use of capacitors in the MAC array, thus allowing the computing module to have a reduced area and suffer from less computation errors. Also proposed is a method of fully taking advantage of data sparsity to lower the ADC block's power consumption.

Abstract: A mixed-signal in-memory computing sub-cell requires only 9 transistors for 1-bit multiplication. In one aspect, there is a computing cell is constructed from a plurality of such sub-cells that share a common computing capacitor and common transistors. As a result, the average number of transistors in each sub-cell is close to 6. Also proposed is a MAC array for performing MAC operations, which includes a plurality of the computing cells each activating the sub-cells therein in a time-multiplexed manner. Also proposed is a differential version of the MAC array with improved computation error tolerance. Also proposed is an in-memory mixed-signal computing module for digitalizing parallel analog outputs of the MAC array and for performing other tasks in the digital domain. An ADC block in the computing module makes full use of capacitors in the MAC array, thus allowing the computing module to have a reduced area and suffer from less computation errors.

Abstract: Apparatus and associated methods relate to a circuit that is configured to keep a comparator input voltage stable. In an illustrative example, the circuit may include a first differential path coupled to a first switched-capacitor network's output, a second differential path coupled to a second switched-capacitor network's output. A comparator may have a first input coupled to the first differential path and a second input coupled to the second differential path. The comparator may be controlled by a clock signal to perform comparison. A first capacitor may be coupled from the clock signal to the first differential signal path and a second capacitor may be coupled from the clock signal to the second differential signal path. By introducing the first capacitor and the second capacitor, the comparator input common-mode may keep stable, and the comparator may be less sensitive to kickback effects.

Abstract: Examples of the present disclosure provide out-of-range voltage detection and protection in integrated circuits (ICs). In some examples, an IC includes an envelope detector, a comparator, and a switch. The envelope detector is configured to generate an envelope signal of a signal and output the envelope signal on an output node of the envelope detector. A first input node of the comparator is coupled to the output node of the envelope detector. The comparator is configured to compare respective signals provided on the first and second input nodes of the comparator and generate a comparison signal in response to the comparison. The comparator is further configured to output the comparison signal on the output node of the comparator. The switch is connected between a protected node and a protection node and is configured to be selectively opened or closed based, at least in part, on the comparison signal.

Abstract: A circuit for digitizing a sum of a first input signal and a plurality of second input signals has a passive adder that sums the second input signals and outputs a summation signal and a multi-bit quantizer circuit. The quantizer circuit compares the summation signal at a first comparator input with a signal at a second comparator input, which is derived from the first input signal and has an appropriate polarity so that the difference between the summation signal and the signal at the second comparator input is indicative of the sum of the first input signal and the plurality of second input signals. The comparator also produces a comparator output signal based on the sum of the first input signal and the plurality of second input signals. The quantizer circuit also has a control logic block for determining a multi-bit representation of the sum from the comparator output signal.

Abstract: A circuit for digitizing a sum of a first input signal and a plurality of second input signals has a passive adder that sums the second input signals and outputs a summation signal and a multi-bit quantizer circuit. The quanitzer circuit compares the summation signal at a first comparator input with a signal at a second comparator input, which is derived from the first input signal and has an appropriate polarity so that the difference between the summation signal and the signal at the second comparator input is indicative of the sum of the first input signal and the plurality of second input signals. The comparator also produces a comparator output signal based on the sum of the first input signal and the plurality of second input signals. The quantizer circuit also has a control logic block for determining a multi-bit representation of the sum from the comparator output signal.