Patents by Inventor Altan Odabasi
Altan Odabasi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11836431Abstract: A chip package system comprising N multiple processor cores can be tested by receiving a data file characterizing the chip package system. Thereafter, simulation testing is conducted for each core for each of Mi . . . j states using the data file such that each core is active in each state while all other cores are inactive. Each simulation test results in a simulation. The simulations are then combined to result in a composite test covering MN*j combinations. Related apparatus, systems, techniques and articles are also described.Type: GrantFiled: June 16, 2021Date of Patent: December 5, 2023Assignee: ANSYS, INC.Inventors: John Lee, Aveek Sarkar, Altan Odabasi, Scott Johnson, Murat Becer, William Mullen
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Publication number: 20230385501Abstract: Methods, systems and media for simulating or analyzing voltage drops in a power distribution network can use an incremental approach to define a portion of a design around a victim to capture a sufficient collection of aggressors that cause appreciable voltage drop on the victim, and then an incremental simulation of just the portion can be performed rather than computing simulated voltage drops across the entire design. This approach can be both computationally efficient and can limit the size of the data used in simulating dynamic voltage drops in the power distribution network. Multiple different portions can be simulated separately in separate processing cores or elements. In one embodiment, a system can provide options of user selected constraints for the simulation to provide better accuracy or use less memory. Better accuracy will normally use a larger set of aggressors for each victim at the expense of using more memory.Type: ApplicationFiled: April 11, 2023Publication date: November 30, 2023Inventors: Altan Odabasi, Scott Johnson, Emrah Acar, Joao Geada
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Patent number: 11663388Abstract: Methods, systems and media for simulating or analyzing voltage drops in a power distribution network can use an incremental approach to define a portion of a design around a victim to capture a sufficient collection of aggressors that cause appreciable voltage drop on the victim, and then an incremental simulation of just the portion can be performed rather than computing simulated voltage drops across the entire design. This approach can be both computationally efficient and can limit the size of the data used in simulating dynamic voltage drops in the power distribution network. Multiple different portions can be simulated separately in separate processing cores or elements. In one embodiment, a system can provide options of user selected constraints for the simulation to provide better accuracy or use less memory. Better accuracy will normally use a larger set of aggressors for each victim at the expense of using more memory.Type: GrantFiled: November 18, 2020Date of Patent: May 30, 2023Assignee: ANSYS, INC.Inventors: Altan Odabasi, Scott Johnson, Emrah Acar, Joao Geada
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Patent number: 11531794Abstract: Methods, systems and media for simulating or analyzing voltage drops in a power distribution network can use an iterative approach to define a portion of a design around a victim to capture a sufficient collection of aggressors that cause appreciable voltage drop on the victim. This approach can be both computationally efficient and accurate and can limit the size of the data used in simulating dynamic voltage drops in the power distribution network.Type: GrantFiled: December 20, 2019Date of Patent: December 20, 2022Assignee: ANSYS, INC.Inventors: Altan Odabasi, Emrah Acar, Sudarsana Reddy Mallu, Tinu Thomas, Mirza Milan, Scott Johnson, Joao Geada, Youlin Liao
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Patent number: 11321513Abstract: Techniques for computer aided design and engineering of integrated circuits can use group identifiers of correlated signals and time delay values when using vectorless dynamic voltage drop (DVD) simulations and when using other types of simulations or analyses of a circuit design. A method in one embodiment can include the operations of: receiving a design representing an electrical circuit that includes a plurality of pins, the plurality of pins including one or more input nodes or one or more output nodes in the electrical circuit; identifying, in the design, one or more groups of pins that are correlated such that, within each identified group, all of the pins in the identified groups switch between voltage states in a correlated way; assigning, for each pin in each identified group, an identifier for the identified group and a time delay value based on the pin's delay from an initial point in the identified group's logic chain to the pin.Type: GrantFiled: November 10, 2020Date of Patent: May 3, 2022Assignee: ANSYS, INC.Inventors: Joao Geada, Emrah Acar, Altan Odabasi, Scott Johnson
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Publication number: 20210350059Abstract: A chip package system comprising N multiple processor cores can be tested by receiving a data file characterizing the chip package system. Thereafter, simulation testing is conducted for each core for each of M, states using the data file such that each core is active in each state while all other cores are inactive. Each simulation test results in a simulation. The simulations are then combined to result in a composite test covering MN8j combinations. Related apparatus, systems, techniques and articles are also described.Type: ApplicationFiled: June 16, 2021Publication date: November 11, 2021Inventors: John LEE, Aveek SARKAR, Altan ODABASI, Scott JOHNSON, Murat BECER, William MULLEN
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Patent number: 11042681Abstract: A chip package system comprising N multiple processor cores can be tested by receiving a data file characterizing the chip package system. Thereafter, simulation testing is conducted for each core for each of Mi . . . j states using the data file such that each core is active in each state while all other cores are inactive. Each simulation test results in a simulation. The simulations are then combined to result in a composite test covering MN*j combinations. Related apparatus, systems, techniques and articles are also described.Type: GrantFiled: March 22, 2018Date of Patent: June 22, 2021Assignee: Ansys, Inc.Inventors: John Lee, Aveek Sarkar, Altan Odabasi, Scott Johnson, Murat Becer, William Mullen
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Patent number: 10990731Abstract: This disclosure describes methods, systems and media for analyzing voltage drops in a power delivery network in a simulated design of an electrical circuit. In one embodiment, a system determines, for a victim element (“victim”), a voltage drop caused by each aggressor element (“aggressor”) in a set of aggressors in the design and creates a data structure that includes, for each victim, at least one of: (1) each voltage drop caused by each aggressor in the set of aggressors or (2) a sum of the voltage drops on the victim caused by all of the aggressors in the set of aggressors. The system can then compute a set of simulations based on random inputs to generate a distribution of possible voltage drops for each victim using data in the data structure.Type: GrantFiled: December 20, 2019Date of Patent: April 27, 2021Assignee: ANSYS, INC.Inventors: Altan Odabasi, Emrah Acar, Sudarsana Reddy Mallu, Tinu Thomas, Mirza Milan, Scott Johnson, Joao Geada
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Patent number: 9286427Abstract: Described herein are systems and methods for a partitioned extraction-simulation technique that efficiently combines a partitioned extraction technique and a partitioned simulation technique by removing and not performing particular steps of the techniques to provide a more efficient netlist extraction and circuit simulation process. In some embodiments, a plurality of circuit simulators directly receive and process a plurality of sub-region netlists that are based on a spatial partitioning of the IC layout. In further embodiments, an EDA hybrid cloud system is implemented using pipelining and serializing of memory data. In these embodiments, an overall EDA process is divided into a plurality of pipelined stages to accelerate the computational speed of the overall EDA process. In further embodiments, EDA data is transferred, over a network, from a memory of one computer system directly to a memory of another computer system by serializing the EDA data.Type: GrantFiled: March 15, 2013Date of Patent: March 15, 2016Assignee: Gear Design SolutionsInventors: Altan Odabasi, Murat Becer, Mustafa Yazgan, Lei Yin, John Lee
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Publication number: 20150379183Abstract: Described herein are systems and methods for a partitioned extraction-simulation technique that efficiently combines a partitioned extraction technique and a partitioned simulation technique by removing and not performing particular steps of the techniques to provide a more efficient netlist extraction and circuit simulation process. In some embodiments, a plurality of circuit simulators directly receive and process a plurality of sub-region netlists that are based on a spatial partitioning of the IC layout. In further embodiments, an EDA hybrid cloud system is implemented using pipelining and serializing of memory data. In these embodiments, an overall EDA process is divided into a plurality of pipelined stages to accelerate the computational speed of the overall EDA process. In further embodiments, EDA data is transferred, over a network, from a memory of one computer system directly to a memory of another computer system by serializing the EDA data.Type: ApplicationFiled: June 8, 2015Publication date: December 31, 2015Inventors: Altan Odabasi, Murat Becer, Mustafa Yazgan, Lei Yin, John Lee
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Patent number: 9053278Abstract: Described herein are systems and methods for a partitioned extraction-simulation technique that efficiently combines a partitioned extraction technique and a partitioned simulation technique by removing and not performing particular steps of the techniques to provide a more efficient netlist extraction and circuit simulation process. In some embodiments, a plurality of circuit simulators directly receive and process a plurality of sub-region netlists that are based on a spatial partitioning of the IC layout. In further embodiments, an EDA hybrid cloud system is implemented using pipelining and serializing of memory data. In these embodiments, an overall EDA process is divided into a plurality of pipelined stages to accelerate the computational speed of the overall EDA process. In further embodiments, EDA data is transferred, over a network, from a memory of one computer system directly to a memory of another computer system by serializing the EDA data.Type: GrantFiled: March 15, 2013Date of Patent: June 9, 2015Assignee: Gear Design SolutionsInventors: Altan Odabasi, Murat Becer, Mustafa Yazgan, Lei Yin, John Lee