Abstract: A variable word length data memory. The data memory disclosed has standard 16-bit word memory operation. The variable word length enables increased software efficiency in implementing software buffers using single memory locations parallel to the memory words as tags. Low-cost, efficient logic processing is enabled through a flag processor instruction set. This instruction set provides direct reference to flag memory, status test flags, and latched condition states.

Abstract: This application describes a method of multiplying numbers represented in multiple-word chains. The multiplication scheme allows for the multiplication of both signed and unsigned numbers of varying lengths. The multiplier block 30 executes a 17-bit by 17-bit two's complement multiply and multiply-accumulate in a single instruction cycle. A 4-bit shift value register with a 4 to 16 bit decoder 35 allows the multiplier to do a 1-16 bit barrel shift on either a 16-bit operand or an (N×16)-bit chain operand.

Abstract: Specialized microprocessor hardware 10 and a specialized instruction set that provides efficient data processing operations on long word length or bit length data. Instructions that manipulate data include a reserved bit-switch (in the form of a two bit field) whose status (A0) causes the instruction to be executed once to operate on a single word of data, or whose status (A0S) causes the instruction to be repeatedly executed as the instruction operates on a chain or list of sequential data, for example a data chain including N 16-bit words of data, wherein N is an integer. Every instruction word that manipulates data has a reserved bit switch that will cause the instruction to be executed either once operating on single word data or as a repeated execution of the same instruction operating on a chain or list of sequential data (n words).

Abstract: A variable word length data memory. The data memory disclosed has standard 16-bit word memory operation. The variable word length enables increased software efficiency in implementing software buffers using single memory locations parallel to the memory words as tags. Low-cost, efficient logic processing is enabled through a flag processor instruction set. This instruction set provides direct reference to flag memory, status test flags, and latched condition states.

Abstract: A variable word length data memory. The data memory disclosed has standard 16-bit word memory operation. The variable word length enables increased software efficiency in implementing software buffers using single memory locations parallel to the memory words as tags. Low-cost, efficient logic processing is enabled through a flag processor instruction set. This instruction set provides direct reference to flag memory, status test flags, and latched condition states.

Abstract: This application describes a method of protecting data and program code stored in an EPROM array from piracy. The security scheme allows for segmentation of the array to protect one section of the array from reading while programming a non-secure section. The security scheme also allows for protection of the entire array after programming is complete. It also incorporates a device to prevent tampering with the segmentation registers and a means to prevent circumvention of the security scheme even when the processor is in one or more of its test modes.

Abstract: An oscillator circuit which demonstrates stable operation over a wide range of supply voltages and process variations. A latch circuit is controlled utilizing a timing capacitor. A constant current source is applied alternately to opposite sides of the timing capacitor through a series of switching gates which bootstrap the voltage across the timing capacitor, with the switching gates being controlled by the output of the latch circuit.