Abstract: A resistive memory device, such as a BMC ReRAM device, includes at least one resistive memory element which contains a carbon barrier material portion and a resistive memory material portion that is disposed between a first electrode and a second electrode.

Abstract: A resistive memory device, such as a BMC ReRAM device, includes at least one resistive memory element which contains a carbon barrier material portion and a resistive memory material portion that is disposed between a first electrode and a second electrode.

Abstract: A method is provided that includes forming a bit line above a substrate, forming a word line above the substrate, and forming a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a non-volatile memory material coupled in series with an isolation element. The isolation element includes a first portion disposed between a first electrode and a second electrode, the first electrode includes a first material having a first work function, the second electrode includes a second material having second work function, and the first work function does not equal the second work function.

Abstract: A method is provided that includes providing a memory device including a first word line, a vertical bit line, a non-volatile memory material disposed between the first word line and the vertical bit line, and a memory cell disposed between the first word line and the vertical bit line. The first word line has a first height. The method further includes forming one or more conductive filaments in the memory cell. The one or more conductive filaments are substantially confined to a filament region having a second height less than the first height and disposed substantially about a vertical center of the memory cell.

Abstract: A method is provided that includes providing a memory device including a first word line, a vertical bit line, a non-volatile memory material disposed between the first word line and the vertical bit line, and a memory cell disposed between the first word line and the vertical bit line. The first word line has a first height. The method further includes forming one or more conductive filaments in the memory cell. The one or more conductive filaments are substantially confined to a filament region having a second height less than the first height and disposed substantially about a vertical center of the memory cell.

Abstract: A transistor structure, such as a Double-gated FET (DG FET), that has been modified to include a charge-trapping region used to store either 2- or 4-bits of information. The charge-trapping region can, for example, be embedded in the gate dielectric stack underneath each gate electrode, or placed on the sidewalls of each gate electrode.