Abstract: A data buffer makes use of a plurality of buffer storage cells into which serial bit streams are sequentially written, in order to obtain correction for phase jitter. A write clock signal is derived from the serial bit stream and is used to sequentially write the digits into the cells. A stable clock source is used to provide the basic timing for sequentially reading the bits out from the buffer storage cells, and a logic circuit is used in conjunction therewith to obtain the retimed serial bit stream. The write and read timing signals should have a maximum time separation to allow for maximum correction of phase jitter, and it is critical that the write and read signals should alternate. A monitor and reset circuit compares a selected write signal with a selected read signal and, where a violation of the alternating write-read condition occurs, the circuit resets the write timing and holds it until the read timing has attained a particular state.

Abstract: In a digital communication system, apparatus for upconverting the bit rate, f.sub.1, of a digital data source to permit digital transmission at a bit rate f.sub.2, where f.sub.2 > f.sub.1. Pulse stuffing techniques are used to insert a fixed number of time slots in the digital data signal such that the ratio of information time slots to stuffed time slots remains constant. The upconverted signal, consisting of nonredundant data bits and stuffed time slots, is interleaved with framing bits prior to transmission over a digital facility. The framing bits provide the synchronization information to enable the receiver to identify the added time slots and to selectively remove the information data bits from the transmitted line signal. The desired data bits are then restored to their original f.sub.1 bit rate.

Abstract: Disclosed is a digital multiplexer which combines N parallel bit-synchronized digital signals, each of bit rate f.sub.1, into a single composite line signal of bit rate f.sub.2, where f.sub.2 > Nf.sub.1. Before the individual bits are interleaved, each digital signal is converted to a submultiple of the line frequency, f.sub.2. By inserting gaps having a predetermined duration and occurring at a fixed rate into each of the N digital signals, the bit rate f.sub.1 of each bit stream is increased to f.sub.2 /N. This is done without sampling any bit more than once. A multiplexer sequentially interleaves each bit from the N converted bit streams along with the gaps in each bit stream, forming the composite signal of bit rate f.sub.2. The interleaved gaps form empty time slots in the composite signal into which one or more signaling bits are added. Some of the added signaling bits carry framing information to lock the transmitter and receiver together.

Abstract: A time-division multiplexing system wherein N parallel digital signals having an average bit rate of f.sub.1 are interleaved by a multiplexer to form a single composite line signal of bit rate f.sub.2, where f.sub.2 > NF.sub.1. Prior to multiplexing, signal gaps having a predetermined duration and having a fixed repetition rate are inserted into each of the N parallel signals. Adding gaps to each digital signal permits the bit rate between gaps to be increased to f.sub.2 /N, a submultiple of the composite line signal bit rate. The gap duration and their occurrence is such so as to maintain the average bit rate of each digital signal at f.sub.1. Each digital signal with the added gaps is then interleaved to form the composite line signal having the desired bit rate of f.sub.2. The interleaved gaps form empty time slots in the composite signal into which one or more signaling bits are added.