Patents by Inventor Amandeep Kaur
Amandeep Kaur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240111656Abstract: Techniques and mechanisms for circuitry of a processor to determine a count of prefetch instructions which have been retired, or are designated for retirement. In an embodiment, a performance monitoring unit (PMU) monitors the execution of an instruction sequence by a core of said processor. The PMU detects the retirement of a first instruction, and further makes a first determination that the instruction is of a prefetch instruction type. Based on the first determination, counter circuitry of the processor updates a count of one or more instruction retirements, wherein each such retired instruction is of the prefetch instruction type. The PMU further makes a second determination that another retired second instruction is of a non-prefetch instruction type. In another embodiment, the counter circuitry prevents any updating of that same count based on the second determination.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Ahmad Yasin, Anton Hanna, Yuval Alon, Amandeep Kaur
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Patent number: 11521703Abstract: Various implementations described herein are related to a method for identifying multi-bank memory architecture having multiple banks including a first bank and a second bank. The method may receive a faulty row address having a faulty bank selection bit, and also, the method may select the first bank or the second bank for row redundancy operations based on the faulty bank selection bit.Type: GrantFiled: March 31, 2021Date of Patent: December 6, 2022Assignee: Arm LimitedInventors: Amandeep Kaur, Andy Wangkun Chen, Penaka Phani Goberu, Khushal Gelda
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Publication number: 20220319632Abstract: Various implementations described herein are related to a method for identifying multi-bank memory architecture having multiple banks including a first bank and a second bank. The method may receive a faulty row address having a faulty bank selection bit, and also, the method may select the first bank or the second bank for row redundancy operations based on the faulty bank selection bit.Type: ApplicationFiled: March 31, 2021Publication date: October 6, 2022Inventors: Amandeep Kaur, Andy Wangkun Chen, Penaka Phani Goberu, Khushal Gelda
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Publication number: 20200345633Abstract: A pharmaceutical composition comprising a muscarinic antagonist and an adenosine antagonist for topical or ophthalmic application, and ophthalmic devices containing or delivering the same, and methods of using the same, for controlling and/or reducing the progression of myopia.Type: ApplicationFiled: November 2, 2018Publication date: November 5, 2020Inventors: Minas Theodore Coroneo, Monica Jong, Padmaja Rajagopal Sankaridurg, Earl Leo Smith, III, Amandeep Kaur
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Patent number: 10725104Abstract: Disclosed is an apparatus including a datapath and a test circuit. The datapath is configured to transfer data between a memory core and an IO interface. The datapath includes a plurality of circuits, and a memory core interface. The plurality of circuits operates according to a supply voltage. The test circuit is coupled to the datapath, and configured to determine, from a set of operable voltage levels of the supply voltage, a first minimum operable voltage level for the datapath to operate for the data traversing the datapath at a first frequency.Type: GrantFiled: December 22, 2017Date of Patent: July 28, 2020Assignee: SanDisk Technologies LLCInventors: Amandeep Kaur, Sridhar Yadala, Jayanth Mysore Thimmaiah, Ravindra Arjun Madpur
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Patent number: 10552169Abstract: Apparatuses, systems, methods, and computer program products are disclosed for on-die signal calibration. A calibration circuit on an integrated circuit device receives data from an active data path of the integrated circuit device and detects a variation in the received data from a calibration data pattern. An adjustment circuit on an integrated circuit device reduces a delay of an active data path of the integrated circuit device in response to detecting a first variation in received data. An adjustment circuit on an integrated circuit device increases a delay of an active data path of the integrated circuit device in response to detecting a second variation in received data.Type: GrantFiled: September 18, 2017Date of Patent: February 4, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Ravindra Arjun Madpur, Amandeep Kaur
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Patent number: 10528286Abstract: Apparatuses, systems, methods, and computer program products are disclosed for accessing non-volatile memory. An apparatus includes one or more memory die. A memory die includes an array of non-volatile memory cells, a set of ports, and an on-die controller. A set of ports includes a first port and a second port. A first port includes a first plurality of electrical contacts and a second port includes a second plurality of electrical contacts. An on-die controller communicates via a set of ports to receive command and address information and to transfer data for data operations on an array of non-volatile memory cells. An on-die controller uses a first port to receive command and address information and to transfer data. An on-die controller uses a second port to transfer data but not to receive command and address information.Type: GrantFiled: August 7, 2017Date of Patent: January 7, 2020Assignee: SanDisk Technologies LLCInventors: Ravindra Arjun Madpur, Amandeep Kaur
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Patent number: 10528255Abstract: Apparatuses, systems, methods, and computer program products are disclosed for accessing non-volatile memory. An apparatus includes one or more memory die. A memory die includes an array of non-volatile memory cells, a set of ports, and an on-die controller. The set of ports includes a first port and a second port. The first port includes a first plurality of electrical contacts and the second port includes a second plurality of electrical contacts. The on-die controller communicates via the set of ports to receive command and address information and to transfer data for a data operation on the array of non-volatile memory cells. The on-die controller uses the first port and the second port in a first mode and uses the first port without the second port in a second mode. The second mode provides compatibility with an interface of a legacy type of memory die.Type: GrantFiled: November 30, 2016Date of Patent: January 7, 2020Assignee: SanDisk Technologies LLCInventors: Jiwang Lee, Anil Pai, Tianyu Tang, Ravindra Arjun Madpur, Amandeep Kaur, Ragul Kumar Krishnan, Venkata Kolagatla
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Patent number: 10528267Abstract: Apparatuses, systems, methods, and computer program products are disclosed for queueing commands for storage operations. An apparatus includes a command queue configured to queue storage commands received at a storage device and a controller for the storage device. A controller is configured to receive a storage command on a first port of a storage device. A controller is configured to queue a received storage command as an entry in a command queue. An entry in a command queue indicates a type of a received storage command. A controller is configured to service a received storage command from a command queue on a second port of a storage device based on a type of the received storage command indicated by an entry in the command queue associated with the received storage command.Type: GrantFiled: June 29, 2017Date of Patent: January 7, 2020Assignee: SanDisk Technologies LLCInventors: Nidhi Batra, Ravindra Arjun Madpur, Amandeep Kaur
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Publication number: 20190195948Abstract: Disclosed is an apparatus including a datapath and a test circuit. The datapath is configured to transfer data between a memory core and an IO interface. The datapath includes a plurality of circuits, and a memory core interface. The plurality of circuits operates according to a supply voltage. The test circuit is coupled to the datapath, and configured to determine, from a set of operable voltage levels of the supply voltage, a first minimum operable voltage level for the datapath to operate for the data traversing the datapath at a first frequency.Type: ApplicationFiled: December 22, 2017Publication date: June 27, 2019Inventors: Amandeep Kaur, Sridhar Yadala, Jayanth Mysore Thimmaiah, Ravindra Arjun Madpur
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Patent number: 10204668Abstract: Disclosed is a system including a memory timing calibration circuit to calibrate a strobe signal of a memory device and a method of calibrating the strobe signal. The memory timing calibration circuit includes a difference signal generator coupled to a strobe signal generator and an external control circuit. The difference signal generator is configured to generate a difference signal indicating a time difference between the strobe signal from the strobe signal generator and an external clock signal from the external control circuit. The memory timing calibration circuit further includes a delay circuit coupled to the difference signal generator and the external control circuit. The delay circuit is configured to generate a modified external clock signal by delaying the external clock signal by a delay determined based at least in part on the difference signal.Type: GrantFiled: October 9, 2017Date of Patent: February 12, 2019Assignee: SanDisk Technologies LLCInventors: Sneha Bhatia, Amandeep Kaur, Ravindra Arjun Madpur
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Publication number: 20180267810Abstract: Apparatuses, systems, methods, and computer program products are disclosed for on-die signal calibration. A calibration circuit on an integrated circuit device receives data from an active data path of the integrated circuit device and detects a variation in the received data from a calibration data pattern. An adjustment circuit on an integrated circuit device reduces a delay of an active data path of the integrated circuit device in response to detecting a first variation in received data. An adjustment circuit on an integrated circuit device increases a delay of an active data path of the integrated circuit device in response to detecting a second variation in received data.Type: ApplicationFiled: September 18, 2017Publication date: September 20, 2018Applicant: SanDisk Technologies LLCInventors: RAVINDRA ARJUN MADPUR, AMANDEEP KAUR
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Publication number: 20180136843Abstract: Apparatuses, systems, methods, and computer program products are disclosed for accessing non-volatile memory. An apparatus includes one or more memory die. A memory die includes an array of non-volatile memory cells, a set of ports, and an on-die controller. The set of ports includes a first port and a second port. The first port includes a first plurality of electrical contacts and the second port includes a second plurality of electrical contacts. The on-die controller communicates via the set of ports to receive command and address information and to transfer data for a data operation on the array of non-volatile memory cells. The on-die controller uses the first port and the second port in a first mode and uses the first port without the second port in a second mode. The second mode provides compatibility with an interface of a legacy type of memory die.Type: ApplicationFiled: November 30, 2016Publication date: May 17, 2018Applicant: SanDisk Technologies LLCInventors: Jiwang Lee, Anil Pai, Tianyu Tang, Ravindra Arjun Madpur, Amandeep Kaur, Ragul Kumar Krishnan, Venkata Kolagatla
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Publication number: 20180136851Abstract: Apparatuses, systems, methods, and computer program products are disclosed for queueing commands for storage operations. An apparatus includes a command queue configured to queue storage commands received at a storage device and a controller for the storage device. A controller is configured to receive a storage command on a first port of a storage device. A controller is configured to queue a received storage command as an entry in a command queue. An entry in a command queue indicates a type of a received storage command. A controller is configured to service a received storage command from a command queue on a second port of a storage device based on a type of the received storage command indicated by an entry in the command queue associated with the received storage command.Type: ApplicationFiled: June 29, 2017Publication date: May 17, 2018Applicant: SanDisk Technologies LLCInventors: NIDHI BATRA, RAVINDRA ARJUN MADPUR, AMANDEEP KAUR
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Publication number: 20180136878Abstract: Apparatuses, systems, methods, and computer program products are disclosed for accessing non-volatile memory. An apparatus includes one or more memory die. A memory die includes an array of non-volatile memory cells, a set of ports, and an on-die controller. A set of ports includes a first port and a second port. A first port includes a first plurality of electrical contacts and a second port includes a second plurality of electrical contacts. An on-die controller communicates via a set of ports to receive command and address information and to transfer data for data operations on an array of non-volatile memory cells. An on-die controller uses a first port to receive command and address information and to transfer data. An on-die controller uses a second port to transfer data but not to receive command and address information.Type: ApplicationFiled: August 7, 2017Publication date: May 17, 2018Applicant: SanDisk Technologies LLCInventors: Ravindra Arjun Madpur, Amandeep Kaur
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Publication number: 20140212494Abstract: A method of treating constipation is disclosed. The method includes administering starch-entrapped microbeads.Type: ApplicationFiled: September 24, 2012Publication date: July 31, 2014Inventors: Bruce Hamaker, Ali Keshavarzian, Mark D. Cisneros, Amandeep Kaur, Heather Rasmussen