Abstract: Various implementations described herein refer to an integrated circuit having first clock circuitry that receives a first clock signal and provides sampled offset pulses associated with the first clock signal when enabled with enable signals. The integrated circuit may include second clock circuitry that receives a second clock signal and provides the enable signals to the first clock circuitry based on the second clock signal. The integrated circuit may include fault detector circuitry that receives the sampled offset pulses from the first clock circuitry, receives the enable signals from the second clock circuitry, and provides one or more error flags for detected faults of the first clock signal based on the sampled offset pulses from the first clock circuitry and based on the enable signals from the second clock circuitry.

Abstract: Various implementations described herein refer to an integrated circuit having first clock circuitry that receives a first clock signal and provides sampled offset pulses associated with the first clock signal when enabled with enable signals. The integrated circuit may include second clock circuitry that receives a second clock signal and provides the enable signals to the first clock circuitry based on the second clock signal. The integrated circuit may include fault detector circuitry that receives the sampled offset pulses from the first clock circuitry, receives the enable signals from the second clock circuitry, and provides one or more error flags for detected faults of the first clock signal based on the sampled offset pulses from the first clock circuitry and based on the enable signals from the second clock circuitry.

Abstract: Various implementations described herein refer to an integrated circuit having a clock generator providing a clock signal. The integrated circuit may include a block having a block boundary, and the block receives the clock signal from the clock generator and provides the clock signal along a clock-tree. The integrated circuit may include a plurality of sub-blocks disposed within the block boundary of the block, and each sub-block of the plurality of sub-blocks receives the clock signal from within the block boundary of the block via the clock-tree, and diverges the clock signal into a first clock signal and a second clock signal from within a sub-block boundary of each sub-block.

Abstract: A digital bus includes a transmitter unit, a receiver unit, and a transmission medium to couple the transmitter unit to the receiver unit and to provide a path for exchanging information between the transmitter unit and the receiver unit. The receiver unit includes a first-in-first-out (FIFO) unit and a synchronizer unit for receiving information from the transmitter unit. The synchronizer unit receives a plurality of write clock signals and a reset signal and generates a read reset signal positioned with respect to the plurality write clock signals and a sample clock signal. The read reset signal has a latency with respect to each of the plurality of write reset signals of between 0 and 1 clock cycles.

Abstract: A simultaneous bidirectional port coupled to a bus includes a synchronization circuit that synchronizes the port with another simultaneous data port coupled to the same bus. The synchronization circuit includes an output driver having an imbalanced output impedance, and includes a receiver with input hysteresis. The input hysteresis of the receiver is not satisfied unless both drivers with imbalanced output impedance coupled to the bus assert an output signal. Each driver asserts a signal on the bus when initialization of the corresponding simultaneous bidirectional port is complete. When both simultaneous bidirectional ports are initialized, the hysteresis of the receivers is satisfied, and each port is notified that both have been initialized.

Abstract: A multiply-accumulate circuit includes a compressor tree to generate a product with a binary exponent and a mantissa in carry-save format. The product is converted into a number having a three bit exponent and a fifty-seven bit mantissa in carry-save format for accumulation. An adder circuit accumulates the converted products in carry-save format. Because the products being summed are in carry-save format, post-normalization is avoided within the adder feedback loop. The adder operates on floating point number representations having exponents with a least significant bit weight of thirty-two, and exponent comparisons within the adder exponent path are limited in size. Variable shifters are avoided in the adder mantissa path. A single mantissa shift of thirty-two bits is provided by a conditional shifter.

Abstract: A digital bus includes a transmitter unit, a receiver unit, and a transmission medium to couple the transmitter unit to the receiver unit and to provide a path for exchanging information between the transmitter unit and the receiver unit. The receiver unit includes a first-in-first-out (FIFO) unit and a synchronizer unit for receiving information from the transmitter unit. The synchronizer unit receives a plurality of write clock signals and a reset signal and generates a read reset signal positioned with respect to the plurality write clock signals and a sample clock signal. The read reset signal has a latency with respect to each of the plurality of write reset signals of between 0 and 1 clock cycles.

Abstract: A digital bus includes a transmitter unit, a receiver unit, and a transmission medium to couple the transmitter unit to the receiver unit and to provide a path for exchanging information between the transmitter unit and the receiver unit. The receiver unit includes a first-in-first-out (FIFO) unit and a synchronizer unit for receiving information from the transmitter unit. The synchronizer unit receives a plurality of write clock signals and a reset signal and generates a read reset signal positioned with respect to the plurality write clock signals and a sample clock signal. The read reset signal has a latency with respect to each of the plurality of write reset signals of between 0 and 1 clock cycles.

Abstract: A floating point adder circuit includes an exponent path and a mantissa path. The exponent path includes a comparator to compare two three-bit exponents. The two exponents are each incremented, and a resultant exponent is chosen from one of the two original exponents or one of the incremented exponents. The mantissa path includes an adder to add mantissas, and an adder bypass path to select one of the mantissas in lieu of performing an addition. The mantissa path also includes constant shifters that conditionally shift the mantissas right by thirty-two bit positions.

Abstract: A multiply-accumulate circuit includes a compressor tree to generate a product with a binary exponent and a mantissa in carry-save format. The product is converted into a number having a three bit exponent and a fifty-seven bit mantissa in carry-save format for accumulation. An adder circuit accumulates the converted products in carry-save format. Because the products being summed are in carry-save format, post-normalization is avoided within the adder feedback loop. The adder operates on floating point number representations having exponents with a least significant bit weight of thirty-two, and exponent comparisons within the adder exponent path are limited in size. Variable shifters are avoided in the adder mantissa path. A single mantissa shift of thirty-two bits is provided by a conditional shifter.

Abstract: A multiply-accumulate circuit includes a compressor tree to generate a product with a binary exponent and a mantissa in carry-save format. The product is converted into a number having a three bit exponent and a fifty-seven bit mantissa in carry-save format for accumulation. An adder circuit accumulates the converted products in carry-save format. Because the products being summed are in carry-save format, post-normalization is avoided within the adder feedback loop. The adder operates on floating point number representations having exponents with a least significant bit weight of thirty-two, and exponent comparisons within the adder exponent path are limited in size. Variable shifters are avoided in the adder mantissa path. A single mantissa shift of thirty-two bits is provided by a conditional shifter.

Abstract: A multiply-accumulate circuit includes a compressor tree to generate a product with a binary exponent and a mantissa in carry-save format. The product is converted into a number having a three bit exponent and a fifty-seven bit mantissa in carry-save format for accumulation. An adder circuit accumulates the converted products in carry-save format. Because the products being summed are in carry-save format, post-normalization is avoided within the adder feedback loop. The adder operates on floating point number representations having exponents with a least significant bit weight of thirty-two, and exponent comparisons within the adder exponent path are limited in size. Variable shifters are avoided in the adder mantissa path. A single mantissa shift of thirty-two bits is provided by a conditional shifter.

Abstract: A multiply-accumulate circuit includes a compressor tree to generate a product with a binary exponent and a mantissa in carry-save format. The product is converted into a number having a three bit exponent and a fifty-seven bit mantissa in carry-save format for accumulation. An adder circuit accumulates the converted products in carry-save format. Because the products being summed are in carry-save format, post-normalization is avoided within the adder feedback loop. The adder operates on floating point number representations having exponents with a least significant bit weight of thirty-two, and exponent comparisons within the adder exponent path are limited in size. Variable shifters are avoided in the adder mantissa path. A single mantissa shift of thirty-two bits is provided by a conditional shifter.

Abstract: A floating point adder circuit includes an exponent path and a mantissa path. The exponent path includes a comparator to compare two three-bit exponents. The two exponents are each incremented, and a resultant exponent is chosen from one of the two original exponents or one of the incremented exponents. The mantissa path includes an adder to add mantissas, and an adder bypass path to select one of the mantissas in lieu of performing an addition. The mantissa path also includes constant shifters that conditionally shift the mantissas right by thirty-two bit positions.

Abstract: A current reference with reduced sensitivity to process variations includes a variable resistor and a control transistor. The control transistor has a generated current from source-to-drain that first passes through the variable resistor. The control transistor has a reference voltage applied to the gate, and the source-to-gate voltage is a function of the reference voltage and the voltage drop across the variable resistor. A control loop circuit measures the generated current and modifies the resistance value of the variable resistor in response. An external precision resistor is used to measure the generated current, and current variations as a result of process variations are reduced.

Abstract: A current reference with reduced sensitivity to process variations includes two current sources. The first current source has an output current that is sensitive to process variations. The second current source has, as a component of its input current, the output current of the first current source. The input current to the second current source is substantially constant because the process dependent component has been removed by the output current of the first current source. Variable resistors internal to the current source are set using a control loop circuit and an external resistor.