Abstract: A flip chip integrated circuit package which has a layer of nickel-boron (Ni--B) on the contact pads of the package substrate and a layer of nickel-phosphorus (Ni--P) on the pins of the substrate. A layer of gold is plated onto the layers of nickel. An integrated circuit with a plurality of solder bumps is placed onto the contact pads of the substrate. The package is heated to reflow the solder bumps, gold and nickel-boron into solder joints that attach the integrated circuit to the substrate. The package is then typically shipped and mounted to a printed circuit board by soldering the pins to the board.

Abstract: A package for an integrated circuit that contains a plurality of small circular dielectric spaces which separate vias from a conductive plane of the package. The package has a first internal conductive plane, a second internal conductive plane and a plurality of bond pads located on a top surface of a substrate. The substrate has a plurality of vias that extend through the first conductive plane to couple the second conductive plane to the bond pads. The package has a plurality of concentric dielectric clearance spaces that separate the vias from the first conductive plane. The small concentric spaces optimize the area of the conductive plane to minimize the resistance and maximize the capacitance of the package.

Abstract: An integrated circuit package which contains an integrated circuit that is mounted to a plurality of contact pads located on a top surface of a substrate. The package may also have a number of capacitors that are mounted to the contact pads. The substrate has an internal first power plane and an internal first ground plane located adjacent to the top surface and coupled to the contact pads by a plurality of vias. The power and ground planes are coupled to the capacitors and the integrated circuit, such that the capacitors filter power that is provided to the circuit. Locating the power and ground planes near the top surface minimizes the length of the vias and lowers the self inductance of the package. The contact pads of the capacitors may be arranged in alternating rows of ground and power to increase the mutual inductance and lower the effective inductance of the package.

Abstract: A flip chip integrated circuit package which has a layer of nickel-boron (Ni--B) on the contact pads of the package substrate and a layer of nickel-phosphorus (Ni--P) on the pins of the substrate. A layer of gold is plated onto the layers of nickel. An integrated circuit with a plurality of solder bumps is placed onto the contact pads of the substrate. The package is heated to reflow the solder bumps, gold and nickel-boron into solder joints that attach the integrated circuit to the substrate. The package is then typically shipped and mounted to a printed circuit board by soldering the pins to the board.

Abstract: A package for an integrated circuit that contains a plurality of small circular dielectric spaces which separate vias from a conductive plane of the package. The package has a first internal conductive plane, a second internal conductive plane and a plurality of bond pads located on a top surface of a substrate. The substrate has a plurality of vias that extend through the first conductive plane to couple the second conductive plane to the bond pads. The package has a plurality of concentric dielectric clearance spaces that separate the vias from the first conductive plane. The small concentric spaces optimize the area of the conductive plane to minimize the resistance and maximize the capacitance of the package.