Abstract: Electronic design automation systems, methods, and media are presented for multi-dimension clock gate design in clock tree synthesis. In one embodiment, an input list of clock gate types is accessed, and the list is then used in generating a clock gate matrix. A circuit design with a clock tree is then accessed. The multi-dimensional design involves automatically selecting, for a first clock gate of the routing tree, a first clock gate type from the clock gate matrix based on a size and associated area for the first clock gate type to select a drive strength value for the first clock gate in the routing tree. The first clock gate is then resized to generate a resized first clock gate using the clock gate matrix to adjust a first delay value associated with the first clock gate while maintaining the drive strength value.

Abstract: Aspects of the present disclosure address systems and methods for shortening clock-tree wirelength based on target offsets in connected routes. A clock tree comprising routes that interconnect a plurality of clock-tree instances is accessed from memory. A clock-tree instance is selected for evaluation. A baseline power consumption measurement corresponding to a sub-tree of the clock-tree instance with the clock-tree instance at a first size is determined. An alternative power consumption measurement corresponding to the sub-tree of the clock-tree instance with the clock-tree instance at a second size is determined. Based on determining that the baseline power consumption measurement is less than the alternative power consumption measurement, the clock-tree instance is resized according to the second size.

Abstract: Various embodiments provide for generation of a clock tree for a circuit design using a mix of a set of buffers and a set of inverters. Some embodiments balance use of buffers and inverters such that the generated clock tree leverages buffers to lower driver count and clock tree, and leverages inverters for lower power usage and duty cycles.

Abstract: Systems, methods, media, and other such embodiments described herein relate to trimming cell lists prior to generation of a routing tree for a circuit design. One embodiment involves accessing a cell library including cell data and a cell list for a plurality of cells. Specialized delay cells are removed from the cell list, and remaining cells are analyzed to identify a set of cell characteristics. Cells are then trimmed from the cell list based on comparisons between the cell characteristics of the remaining cells. If certain cells are sufficiently similar, secondary characteristics can be used to further trim the cell list. The trimmed cell list can then be used to generate a routing tree for the circuit design according to associated design criteria.