Patents by Inventor Amir Al-Bayati

Amir Al-Bayati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080254233
    Abstract: Methods of depositing amorphous carbon films on substrates are provided herein. The methods reduce or prevent plasma-induced charge damage to the substrates from the deposition of the amorphous carbon films. In one aspect, an initiation layer of amorphous carbon is deposited at a low RF power level and/or at a low hydrocarbon compound/inert gas flow rate ratio before a bulk layer of amorphous carbon is deposited. After the deposition of the initiation layer, the RF power, hydrocarbon flow rate, and inert gas flow rate may be ramped to final values for the deposition of the bulk layer, wherein the RF power ramp rate is typically greater than the ramp rates of the hydrocarbon compound and of the inert gas.
    Type: Application
    Filed: April 10, 2007
    Publication date: October 16, 2008
    Inventors: KWANGDUK DOUGLAS LEE, Matthew Spuller, Martin Jay Seamons, Wendy H. Yeh, Bok Hoen Kim, Mohamad Ayoub, Amir Al-Bayati, Derek R. Witty, Hichem M'Saad
  • Patent number: 7429532
    Abstract: A method of processing a thin film structure on a semiconductor substrate using an optically writable mask, the method includes placing the substrate in a reactor chamber, the substrate having on its surface a target layer to be exposed to a light source in accordance with a predetermined pattern, depositing an optically writable carbon-containing mask layer on the substrate by (a) introducing a carbon-containing process gas into the chamber, (b) generating a reentrant toroidal RF plasma current in a reentrant path that includes a process zone overlying the workpiece by coupling plasma RF source power to an external portion of the reentrant path, (c) coupling RF plasma bias power or bias voltage to the workpiece.
    Type: Grant
    Filed: August 8, 2005
    Date of Patent: September 30, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Kartik Ramaswamy, Hiroji Hanawa, Biagio Gallo, Kenneth S. Collins, Kai Ma, Vijay Parihar, Dean Jennings, Abhilash J. Mayur, Amir Al-Bayati, Andrew Nguyen
  • Patent number: 7428915
    Abstract: A valve system having high maximum gas flow rate and fine control of gas flow rate, includes a valve housing for blocking gas flow through a gas flow path, a large area opening through said housing having a first arcuate side wall and a small area opening through said housing having a second arcuate side wall, and respective large area and small area rotatable valve flaps in said large area and small area openings, respectively, and having arcuate edges congruent with said first and second arcuate side walls, respectively and defining therebetween respective first and second valve gaps. The first and second valve gaps are sufficiently small to block flow of a gas on one side of said valve housing up to a predetermined pressure limit, thereby obviating any need for O-rings.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: September 30, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Andrew Nguyen, Hiroji Hanawa, Kenneth S. Collins, Kartik Ramaswamy, Amir Al-Bayati, Biagio Gallo
  • Patent number: 7422775
    Abstract: A method of processing a workpiece includes introducing an optical absorber material precursor gas into a chamber containing the workpiece, generating an RF oscillating toroidal plasma current in a reentrant path that includes a process zone overlying the workpiece by applying RF source power, so as to deposit a layer of an optical absorber material on the workpiece, and exposing the workpiece to optical radiation that is at least partially absorbed in the optical absorber layer.
    Type: Grant
    Filed: May 17, 2005
    Date of Patent: September 9, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Kartik Ramaswamy, Hiroji Hanawa, Biagio Gallo, Kenneth S. Collins, Kai Ma, Vijay Parihar, Dean Jennings, Abhilash J. Mayur, Amir Al-Bayati, Andrew Nguyen
  • Publication number: 20080173237
    Abstract: Embodiments described herein generally provide a toroidal plasma source, a plasma channeling device, a showerhead, and a substrate support assembly for use in a plasma chamber. The toroidal plasma source, plasma channeling device, showerhead, and substrate support assembly are adapted to improve the usable lifetime of the plasma chamber, as well as reduce assembly cost, increase the plasma chamber reliability, and improve device yield on the processed substrates.
    Type: Application
    Filed: January 18, 2008
    Publication date: July 24, 2008
    Inventors: Kenneth S. Collins, Andrew N. Nguyen, Kartik Ramaswamy, Hiroji Hanawa, Douglas A. Buchberger, Daniel J. Hoffman, Amir Al-Bayati
  • Patent number: 7393765
    Abstract: Device-enhancing coatings are deposited on CMOS devices by successively masking with photoresist each one of the sets of N-channel and P-channel devices while unmasking or leaving unmasked the other set, and after each step of successively masking one of the sets of devices, carrying out low temperature CVD steps with a toroidal RF plasma current while applying an RF plasma bias voltage. The temperature of the workpiece is held below a threshold photoresist removal temperature. The RF bias voltage is held at a level at which the coating is deposited with a first stress when the unmasked set consists of the P-channel devices and with a second stress when the unmasked set consists of N-channel devices.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: July 1, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Hiroji Hanawa, Kartik Ramaswamy, Kenneth S. Collins, Amir Al-Bayati, Biagio Gallo, Andrew Nguyen
  • Publication number: 20080084650
    Abstract: The present invention generally provides methods and apparatus for monitoring and maintaining flatness of a substrate in a plasma reactor. Certain embodiments of the present invention provide a method for processing a substrate comprising positioning the substrate on an electrostatic chuck, applying an RF power between the an electrode in the electrostatic chuck and a counter electrode positioned parallel to the electrostatic chuck, applying a DC bias to the electrode in the electrostatic chuck to clamp the substrate on the electrostatic chuck, and measuring an imaginary impedance of the electrostatic chuck.
    Type: Application
    Filed: October 3, 2007
    Publication date: April 10, 2008
    Inventors: Ganesh Balasubramanian, Amit Bansal, Eller Juco, Mohamad Ayoub, Hyung-Joon Kim, Karthik Janakiraman, Sudha Rathi, Deenesh Padhi, Martin Seamons, Visweswaren Sivaramakrishnan, Bok Kim, Amir Al-Bayati, Derek Witty, Hichem M'Saad, Anton Baryshnikov, Chiu Chan, Shuang Liu
  • Patent number: 7335611
    Abstract: A method of forming a conductor in a thin film structure on a semiconductor substrate includes forming high aspect ratio openings in a base layer having vertical side walls, depositing a dielectric barrier layer comprising a dielectric compound of a barrier metal on the surfaces of the high aspect ratio openings including the vertical side walls, depositing a metal barrier layer comprising the barrier metal on the first barrier layer, depositing a main conductor species seed layer on the metal barrier layer and depositing a main conductor layer. The method further includes annealing the main conductor layer by (a) directing light from an array of continuous wave lasers into a line of light extending at least partially across the thin film structure, and (b) translating the line of light relative to the thin film structure in a direction transverse to the line of light.
    Type: Grant
    Filed: August 8, 2005
    Date of Patent: February 26, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Kartik Ramaswamy, Hiroji Hanawa, Biagio Gallo, Kenneth S. Collins, Kai Ma, Vijay Parihar, Dean Jennings, Abhilash J. Mayur, Amir Al-Bayati, Andrew Nguyen
  • Publication number: 20080044960
    Abstract: A process for conformally doping through the vertical and horizontal surfaces of a 3-dimensional vertical transistor in a semiconductor-on-insulator structure employs an RF oscillating torroidal plasma current to perform either conformal ion implantation, or conformal deposition of a dopant-containing film which can then be heated to drive the dopants into the transistor. Some embodiments employ both conformal ion implantation and conformal deposition of dopant containing films, and in those embodiments in which the dopant containing film is a pure dopant, the ion implantation and film deposition can be performed simultaneously.
    Type: Application
    Filed: September 18, 2007
    Publication date: February 21, 2008
    Inventors: Amir Al-Bayati, Kenneth Collins, Hiroji Hanawa, Kartik Ramaswamy, Biagio Gallo, Andrew Nguyen
  • Patent number: 7323401
    Abstract: A method of processing a thin film structure on a semiconductor substrate using an optically writable mask includes placing the substrate in a reactor chamber, the substrate having on its surface a target layer to be etched in accordance with a predetermined pattern, and depositing a carbon-containing hard mask layer on the substrate by (a) introducing a carbon-containing process gas into the chamber, (b) generating a reentrant toroidal RF plasma current in a reentrant path that includes a process zone overlying the workpiece by coupling plasma RF source power to an external portion of the reentrant path, and (c) coupling RF plasma bias power or bias voltage to the workpiece. The method further includes photolithographically defining the predetermined pattern in the carbon-containing hard mask layer, and etching the target layer in the presence of the hard mask layer.
    Type: Grant
    Filed: August 8, 2005
    Date of Patent: January 29, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Kartik Ramaswamy, Hiroji Hanawa, Biagio Gallo, Kenneth S. Collins, Kai Ma, Vijay Parihar, Dean Jennings, Abhilash J. Mayur, Amir Al-Bayati, Andrew Nguyen
  • Patent number: 7320734
    Abstract: A system for processing a workpiece includes a plasma immersion ion implantation reactor with an enclosure having a side wall and a ceiling and defining a chamber, and a workpiece support pedestal within the chamber having a workpiece support surface facing the ceiling and defining a process region extending generally across the wafer support pedestal and confined laterally by the side wall and axially between the workpiece support pedestal and the ceiling. The enclosure has at least a first pair of openings at generally opposite sides of the process region, and a first hollow conduit outside the chamber having first and second ends connected to respective ones of the first pair of openings, so as to provide a first reentrant path extending through the conduit and across the process region.
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: January 22, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Kenneth S. Collins, Hiroji Hanawa, Kartik Ramaswamy, Andrew Nguyen, Amir Al-Bayati, Biagio Gallo, Gonzalo Antonio Monroy
  • Publication number: 20080008842
    Abstract: Methods for reducing plasma instability for plasma depositing a dielectric layer are provided. In one embodiment, the method includes providing a substrate in a plasma processing chamber, flowing a gas mixture into the chamber, applying an RF power to an electrode to form a plasma in the chamber, and collecting DC bias information. In another embodiment, the method for plasma processing includes obtaining of DC bias information over a plurality of plasma generation events, and determining an RF power application parameter from the DC bias information.
    Type: Application
    Filed: July 7, 2006
    Publication date: January 10, 2008
    Inventors: Jyr Hong Soo, Matthew Spuller, Michael S. Cox, Martin Jay Seamons, Amir Al-Bayati, Bok Hoen Kim, Hichem M'Saad
  • Patent number: 7312148
    Abstract: A method of forming a barrier layer for a thin film structure on a semiconductor substrate includes forming high aspect ratio openings in a base layer having vertical side walls, depositing a dielectric barrier layer comprising a dielectric compound of a barrier metal on the surfaces of the high aspect ratio openings including the vertical side walls and depositing a metal barrier layer comprising the barrier metal on the first barrier layer. The method further includes reflowing the metal barrier layer by (a) directing light from an array of continuous wave lasers into a line of light extending at least partially across the thin film structure, and (b) translating the line of light relative to the thin film structure in a direction transverse to the line of light.
    Type: Grant
    Filed: August 8, 2005
    Date of Patent: December 25, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Kartik Ramaswamy, Hiroji Hanawa, Biagio Gallo, Kenneth S Collins, Kai Ma, Vijay Parihar, Dean Jennings, Abhilash J. Mayur, Amir Al-Bayati, Andrew Nguyen
  • Patent number: 7312162
    Abstract: A method of depositing a carbon layer on a workpiece includes placing the workpiece in a reactor chamber, introducing a carbon-containing process gas into the chamber, generating a reentrant toroidal RF plasma current in a reentrant path that includes a process zone overlying the workpiece by coupling plasma RF source power to an external portion of the reentrant path, and coupling RF plasma bias power or bias voltage to the workpiece.
    Type: Grant
    Filed: May 17, 2005
    Date of Patent: December 25, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Kartik Ramaswamy, Hiroji Hanawa, Biagio Gallo, Kenneth S. Collins, Kai Ma, Vijay Parihar, Dean Jennings, Abhilash J. Mayur, Amir Al-Bayati, Andrew Nguyen
  • Publication number: 20070288116
    Abstract: Methods, systems, and mediums of controlling a semiconductor manufacturing process are described. The method comprises the steps of measuring at least one critical dimension of at least one device being fabricated on at least one of the plurality of wafers, determining at least one process parameter value on the at least one measured dimension, and controlling at least one semiconductor manufacturing tool to process the at least one of the plurality of wafers based on the at least one parameter value. A variation in the at least one critical dimension causes undesirable variations in performance of the at least one device, and at least one process condition is directed to controlling the processing performed on the plurality of wafers. The at least one manufacturing tool includes at least one of an implanter tool and an annealing tool.
    Type: Application
    Filed: April 17, 2007
    Publication date: December 13, 2007
    Inventors: Amir Al-Bayati, Babak Adibi, Majeed Foad, Sasson Somekh
  • Publication number: 20070287301
    Abstract: Methods of processing films on substrates are provided. In one aspect, the methods comprise treating a patterned low dielectric constant film after a photoresist is removed form the film by depositing a thin layer comprising silicon, carbon, and optionally oxygen and/or nitrogen on the film. The thin layer provides a carbon-rich, hydrophobic surface for the patterned low dielectric constant film. The thin layer also protects the low dielectric constant film from subsequent wet cleaning processes and penetration by precursors for layers that are subsequently deposited on the low dielectric constant film.
    Type: Application
    Filed: March 30, 2007
    Publication date: December 13, 2007
    Inventors: Huiwen Xu, Mei-Yee Shek, Li-Qun Xia, Amir Al-Bayati, Derek Witty, Hichem M'Saad
  • Patent number: 7303982
    Abstract: A method for implanting ions in a surface layer of a workpiece includes placing the workpiece on a workpiece support in a chamber with the surface layer being in facing relationship with a ceiling of the chamber, thereby defining a processing zone between the workpiece and the ceiling, and introducing into the chamber a process gas which includes the species to be implanted in the surface layer of the workpiece. The method further includes generating from the process gas a plasma by inductively coupling RF source power into the processing zone from an RF source power generator through an inductively coupled RF power applicator, and applying an RF bias from an RF bias generator to the workpiece support.
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: December 4, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Kenneth S. Collins, Hiroji Hanawa, Kartik Ramaswamy, Andrew Nguyen, Amir Al-Bayati, Biagio Gallo, Gonzalo Antonio Monroy
  • Patent number: 7294563
    Abstract: A process for conformally doping through the vertical and horizontal surfaces of a 3-dimensional vertical transistor in a semiconductor-on-insulator structure employs an RF oscillating torroidal plasma current to perform either conformal ion implantation, or conformal deposition of a dopant-containing film which can then be heated to drive the dopants into the transistor. Some embodiments employ both conformal ion implantation and conformal deposition of dopant containing films, and in those embodiments in which the dopant containing film is a pure dopant, the ion implantation and film deposition can be performed simultaneously.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: November 13, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Amir Al-Bayati, Kenneth S. Collins, Hiroji Hanawa, Kartik Ramaswamy, Biagio Gallo, Andrew Nguyen
  • Patent number: 7291545
    Abstract: A method of ion implanting a species in a workpiece to a selected ion implantation profile depth includes placing a workpiece having a semiconductor material on an electrostatic chuck in or near a processing region of a plasma reactor chamber and applying a chucking voltage to the electrostatic chuck. The method further includes introducing into the chamber a precursor gas including a species to be ion implanted in the workpiece and applying an RF bias to the electrostatic chuck, the RF bias having a bias level corresponding to the ion implantation profile depth.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: November 6, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Kenneth S. Collins, Hiroji Hanawa, Kartik Ramaswamy, Andrew Nguyen, Amir Al-Bayati, Biagio Gallo, Gonzalo Antonio Monroy
  • Patent number: 7292428
    Abstract: A lift pin assembly for use in a reactor for processing a workpiece includes plural lift pins extending generally parallel with a lift direction, each of the plural lift pins having a top end for supporting a workpiece and a bottom end. A lift table faces the bottom ends of the pins and is translatable in a direction generally parallel with the lift direction. A small force detector senses a force exerted by the lift pins that is sufficiently large to indicate a chucked wafer and sufficiently small to avoid dechucking a wafer. A large force detector senses a force exerted by the lift pins in a range sufficient to de-chuck the wafer.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: November 6, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Hiroji Hanawa, Andrew Nguyen, Kenneth S. Collins, Kartik Ramaswamy, Biagio Gallo, Amir Al-Bayati