Abstract: An apparatus and method utilizing an efficient forward error correction (FEC), targeted for processing optical transport network (OTN) signals having transmission rates in excess of 10 Gbps. The FEC uses an advanced implementation of the Bose Chaudhuri Hocquenghem (BCH) code. The use of the BCH code for the FEC improves the performance over prior art solutions for both error correction and detection.

Abstract: An apparatus and method utilizing an efficient forward error correction (FEC), targeted for processing optical transport network (CTN) signals having transmission rates in excess of 10 Gbps. The FEC uses an advanced implementation of the Bose Chaudhuri Hocquenghem (BCH) code. The use of the BCH code for the FEC improves the performance over prior art solutions for both error correction and detection.

Abstract: A method and an inter-chip communication port for supporting a concatenated type of a high order SDH/SONET signal, with processing Transport Overhead bytes (TOH) and Path Overhead bytes (POH) thereof, in a structure which comprises a group of chips, wherein each of the chips is capable of supporting a lower order SDH/SONET signal with processing its TOH and POH, while one of them named a master chip is operative to coordinate operation of the remaining chips named slaves so as to cause them working in accord as one unit.

Abstract: A method for detecting troubles in transmission over a layer of connection in an SDH/SONET telecommunication network, the method comprising a step of obtaining periodically transmitted strings having a standard length (16 or 64 bytes), wherein each of the strings is formed using an overhead byte defined in the layer for the purpose; the method also comprises a step of checking the strings by applying to them a BIP16 procedure.

Abstract: A cell bus arbitration system comprises a data bus and a plurality of modules operative for sending data in data cell. The modules are connected to the data bus and each one of the modules is in communication with each one of the other modules via at least one control line such that each one of the modules is capable of receiving control signals generated by each other module. Arbitration logic assigns bus mastery to one of the modules.

Abstract: A method of determining the integrity of a linked list stored in a memory block, comprises the steps of, providing a series of independent bit positions, defining each of the independent bit positions to correspond to one of the cells, setting each of the independent bit positions to a predetermined setting, resetting each of the independent bit positions upon access of its defined corresponding cell, and then, after a predetermined interval testing the independent bit positions. If then any of the independent bit positions have not been reset by the time the test is made, an error condition is set.

Abstract: A method and apparatus for detecting an error rate of a data stream. The data stream is divided into a sequence of blocks, and a detection interval is defined including a predetermined number of blocks in the sequence. For one or more of the blocks in the detection interval, respective error measures are computed responsive to the error rate of the data stream. The one or more blocks in the detection interval are classified as good or bad blocks by comparing the respective error measures to a first threshold. It is estimated that an error condition exists in the data stream by comparing a count of the bad blocks in the interval to a second threshold.

Abstract: A method for mapping and multiplexing of constant bit rate (CBR) signals into optical transport network (OTN) frames is provided. The method, in addition, enables the transportation of data from a plurality of SONET/SDH clients through a single OTN frame. The preferred method thereby enables efficient adoption of SONET/SDH legacy equipment by OTN networks.

Abstract: An apparatus and method for detection of periodic patterns in digital high rate transmission systems. The apparatus generates a synthetic data stream and compares, in parallel, a sample of the generated data to a sample of an input data stream. If the number of mismatches between both sets of data is equal to or below a defined threshold, then a detection signal is asserted. The provided apparatus may be configured to detect any type of pattern.