Abstract: Embodiments of the present disclosure provide a controller hierarchical decoding architecture. For instance, multiple decoder hierarchies are implemented along with use of hierarchies of codes with locality (e.g., larger code length of a hierarchy is composed of local codes from a lower hierarchy). The hierarchical Error Correction Code (ECC) decoding includes multiple hierarchies such as a first hierarchy, a second hierarchy, and additional hierarchies as needed. A first hierarchy includes low-complexity ECC engines, each connected to a NAND channel for computing local codes of low code lengths. A second hierarchy includes higher complexity ECC engines that shares several NAND channels for correcting corrupt data using relatively larger code length (e.g., and the higher complexity ECC engines of the second hierarchy performs decoding operations using more complex decoding algorithms). The larger code length is composed of local codes from a previous hierarchy.

Abstract: A machine-learning (ML) error-correcting code (ECC) controller may include a hard-decision (HD) ECC decoder optimized for high-speed data throughput, a soft-decision (SD) ECC decoder optimized for high-correctability data throughput, and a machine-learning equalizer (MLE) configured to variably select one of the HD ECC decoder or the SD ECC decoder for data throughput. An embodiment of the ML ECC controller may provide speed-optimized HD throughput based on a linear ECC. The linear ECC may be a soft Hamming permutation code (SHPC).

Abstract: An apparatus and method are provided for memory programming, including receiving a first write data unit including a plurality of data bits; programming by at least one pulse the plurality of data bits to the plurality of memory cells; determining if a number of cells successfully programmed by the at least one pulse is less than a threshold; and if the number of cells successfully programmed by the at least one pulse is less than the threshold, compressing a sparse vector of unsuccessfully programmed data bits, receiving another write data unit, concatenating the vector based on the other write data unit, and programming the concatenated vector to another plurality of memory cells.

Abstract: A method for determining an optimal threshold of a nonvolatile memory device, the method including: reading a page from a nonvolatile memory device with a default threshold and attempting to hard decode the page using the default threshold; reading the page two more times with a predetermined offset voltage when the hard decoding fails and attempting to soft decode the page using the default threshold; approximating an empirical distribution of successfully decoded bits with a Gaussian distribution for each level; finding an intersection of the Gaussian distributions; and setting the intersection as a new reading threshold and reading the page again with the new reading threshold.

Abstract: A method of performing division operations in an error correction code includes the steps of receiving an output ??F†{0} wherein F=GF(2r) is a Galois field of 2r elements, ?=?0?i?r?1?i×?i wherein ? is a fixed primitive element of F, and ?i?GF(2), wherein K=GF(2s) is a subfield of F, and {1, ?} is a basis of F in a linear subspace of K; choosing a primitive element ??K, wherein ?=?1+?×?2, ?1=?0?i?s?1?i×?i?K, ?2=?0?i?s?1?i+s×?i?K, and ?=[?0, . . . , ?r?1]T?GF(2)r; accessing a first table with ?1 to obtain ?3=?1?1, computing ?2×?3 in field K, accessing a second table with ?2=?3 to obtain (1+?×?2×?3)?1=?4+?×?5, wherein ??1=(?1×(1+?×?2×?3))?1=?3×(?4+?×?5)=?3×?4+?×?3×?5; and computing products ?3×?4 and ?3×?5 to obtain ??1=?0?i?s?1?i×?i+?·?i?i?s?1?i+s=?i where ?i?GF(2).

Abstract: A memory system including a memory device and a memory controller including a processor. The memory controller is configured to read outputs from the memory cells in response to a read command from a host and to convert the read outputs to a first codeword. The processor performs a first error correcting code (ECC) operation on the first codeword. The processor is further configured to apply, for each selected memory cell among the memory cells, a corresponding one of the read outputs and at least one related feature as input features to a machine learning algorithm to generate a second codeword, and the memory controller is configured to perform a second ECC operation on the second codeword, when the first ECC operation fails.

Abstract: A memory system includes a memory device, and a memory controller including a processor and an internal memory. A computer program including a neural network is stored in the memory system. The processor executes the computer program to extract a voltage level from each of a plurality of memory cells connected to one string select line (SSL), in which the memory cells and the SSL are included in a memory block of the memory device, provide the voltage levels as input to the neural network, and perform noise cancellation on the SSL, using the neural network, by changing at least one of the voltage levels from a first voltage level to a second voltage level. The first voltage level is classified into a first cluster of memory cells, and the second voltage level is classified into a second cluster of memory cells different from the first cluster.

Abstract: A memory system including a memory device and a memory controller including a processor. The memory controller is configured to read outputs from the memory cells in response to a read command from a host and to convert the read outputs to a first codeword. The processor performs a first error correcting code (ECC) operation on the first codeword. The processor is further configured to apply, for each selected memory cell among the memory cells, a corresponding one of the read outputs and at least one related feature as input features to a machine learning algorithm to generate a second codeword, and the memory controller is configured to perform a second ECC operation on the second codeword, when the first ECC operation fails.

Abstract: A method, apparatus, non-transitory computer readable medium, and system for using an error correction code in a memory device with a neural network are described. Embodiments of the method, apparatus, non-transitory computer readable medium, and system may receive a signal from a physical channel, wherein the signal is based on a modulated symbol representing information bits encoded using an error correction coding scheme, extract features from the signal using a feature extractor trained using probability data collected from the physical channel, and decode the information bits with a neural network decoder taking the extracted features as input.

Abstract: A method, apparatus, non-transitory computer readable medium, and system for selecting program voltages for a memory device are described. Embodiments of the method, apparatus, non-transitory computer readable medium, and system may map a set of information bits to voltage levels of one or more memory cells based on a plurality of embedding parameters, program the set of information bits into the one or more memory cells based on the mapping, detect the voltage levels of the one or more memory cells to generate one or more detected voltage levels, and identify a set of predicted information bits based on the one or more detected voltage levels using a neural network comprising a plurality of network parameters, wherein the network parameters are trained together with the embedding parameters.

Abstract: Systems and methods are described for low power error correction coding (ECC) for embedded universal flash storage (eUFS) are described. The systems and methods may include identifying a first element of an algebraic field; generating a plurality of lookup tables for multiplying the first element; multiplying the first element by a plurality of additional elements of the algebraic field, wherein the multiplication for each of the additional elements is performed using an element from each of the lookup tables; and encoding information according to an ECC scheme based on the multiplication.

Abstract: An apparatus and method are provided for memory programming, including receiving a first write data unit including a plurality of data bits; programming by at least one pulse the plurality of data bits to the plurality of memory cells; determining if a number of cells successfully programmed by the at least one pulse is less than a threshold; and if the number of cells successfully programmed by the at least one pulse is less than the threshold, compressing a sparse vector of unsuccessfully programmed data bits, receiving another write data unit, concatenating the vector based on the other write data unit, and programming the concatenated vector to another plurality of memory cells.

Abstract: A memory controller is configured to perform first error correcting code (ECC) encoding on a plurality of first frames of data, generate a plurality of delta syndrome units corresponding, respectively, to the plurality of first frames of data, generate a delta syndrome codeword by performing second ECC encoding on the plurality of delta syndrome units, the delta syndrome codeword including one or more redundancy data units, perform third ECC encoding on at least one second frame of data such that the encoded at least one second frame of data is a first vector of bits, and determine a second vector of bits such that, adding the second vector of bits to the first vector of bits forms a combined vector of bits which is an ECC codeword having a delta syndrome a value of which is pre-fixed based on at least one of the one or more redundancy data units.

Abstract: Systems and methods are described for low power error correction coding (ECC) for embedded universal flash storage (eUFS) are described. The systems and methods may include identifying a first element of an algebraic field; generating a plurality of lookup tables for multiplying the first element; multiplying the first element by a plurality of additional elements of the algebraic field, wherein the multiplication for each of the additional elements is performed using an element from each of the lookup tables; and encoding information according to an ECC scheme based on the multiplication.

Abstract: A mobile electronic device may include a memory device and a memory controller including an error correction code (ECC) encoder to encode data, a constrained channel encoder configured to encode an output of the ECC encoder based on one or more constraints, a reinforcement learning pulse programming (RLPP) component configured to identify a programming algorithm for programming the data to the memory device, an expectation maximization (EM) signal processing component configured to receive a noisy multi-wordline voltage vector from the memory device and classify each bit of the vector with a log likelihood ration (LLR) value, a constrained channel decoder configured to receive a constrained vector from the EM signal processing component and produce an unconstrained vector, and an ECC decoder configured to decode the unconstrained vector. A machine learning interference cancellation component may operate based on or independent of input from the EM signal processing component.

Abstract: A method of denoising intrinsic sneak currents in a PRAM memory array of M wordlines and N bitlines includes receiving, by the PRAM memory array, an input read address; and selecting from a table of wordline distances from a sense-amplifier versus estimated optimal currents for those wordline distances an estimated optimal reference current for a distance closest to the received input read address. The reference current determines whether a read current is ‘0’ or ‘1’ and minimizes a bit error rate due to effects of sneak paths and parasitic elements that distorts the read current.

Abstract: A decoding circuit includes a Bose-Chaudhuri-Hocquenghem (BCH) decoder. The BCH decoder includes a Syndrome stage for generating syndromes based on a BCH encoded word, a Berlekamp-Massey (BM) stage performing a Berlekamp-Massey algorithm on the syndromes to generate Error Location Polynomial (ELP) coefficients, a Chien stage that performs a Chien search on the ELP coefficients using a Fast Fourier Transform (FFT) to generate error bits and iteration information, and a Frame Fixer stage configured to reorder the error bits to be sequential based on the iteration information. The BCH decoder decodes the BCH encoded word using the reordered error bits.

Abstract: A method for storing data within a memory device includes receiving data to be stored. The received data is encoded. The encoded data is stored within the memory device. Encoding the received data includes encoding the data into two or more sub-codewords. Each of the two or more sub-codewords includes a plurality of outer codewords. Two or more of the plurality of outer codewords are grouped to form a larger codeword that is larger than each of the plurality of outer codewords and the larger codeword is constructed to correct errors and/or erasures that are not correctable by the plurality of outer codewords, individually.

Abstract: A NAND memory device that includes a plurality of blocks, each block comprises a plurality of wordlines and an associated agent, and each wordline comprises a plurality of cells and a plurality of voltage levels and an associated agent, and each voltage level comprises an agent. A method of programming the NAND memory device includes receiving, by an agent at a given rank in the plurality of ranks, parameters from a higher rank agent in the hierarchy of ranks and a state from the memory device; determining, by the agent, an action from the parameters and the state; passing the action as parameters to a lower rank agent in the hierarchy of ranks; and updating the agent based on a reward output by the agent, wherein the reward measures a difference between the target voltage levels of the cells and the actual voltage levels programmed to the cells.

Abstract: A memory system includes a memory device, and a memory controller including a processor and an internal memory. A computer program including a neural network is stored in the memory system. The processor executes the computer program to extract a voltage level from each of a plurality of memory cells connected to one string select line (SSL), in which the memory cells and the SSL are included in a memory block of the memory device, provide the voltage levels as input to the neural network, and perform noise cancellation on the SSL, using the neural network, by changing at least one of the voltage levels from a first voltage level to a second voltage level. The first voltage level is classified into a first cluster of memory cells, and the second voltage level is classified into a second cluster of memory cells different from the first cluster.