Abstract: Methods, systems, and computer-readable media for record-by-record live migration using segmentation are disclosed. Migration of a data set comprises, for a record in a segment being migrated, storing a first status indicating that the record is offline in a source data store. An instance of the record is stored in the destination data store, and a second status is stored to indicate that the record is online in the destination. The record is deleted from the source after the second status is stored. During the migration, a read request for the record is received and determined to be associated with the segment being migrated. A response to the read request is generated that comprises an authoritative instance of the record. The instance of the record in the destination is determined to represent the authoritative instance based (at least in part) on the first status and the second status.

Abstract: Various implementations described herein are directed to a device having voltage generator circuitry that provides a temperature-compensated voltage. The device may include amplifier circuitry that receives the temperature-compensated voltage from the voltage generator circuitry and provides an output voltage based on the temperature-compensated voltage. The device may include voltage retention circuitry that receives the output voltage from the amplifier circuitry and provides a retention voltage to memory based on the output voltage.

Abstract: Methods, systems, and computer-readable media for augmenting storage functionality using emulation of storage characteristics are disclosed. An access request for a data set is received. The access request is formatted according to a first protocol associated with a first data store, and the first data store is associated with first storage characteristics. The access request is translated into a translated access request. The translated access request is formatted according to a second protocol associated with a second data store, and the second data store is associated with second storage characteristics differing at least in part from the first storage characteristics. The translated access request is sent to the second data store. The translated access request is performed by the second data store on the data set using emulation of one or more of the first storage characteristics not included in the second storage characteristics.

Abstract: Various implementations described herein refer to an integrated circuit having a first memory structure and a second memory structure. The first memory structure is disposed in a first area of the integrated circuit, and the first memory structure has first memory cells with first transistors. The second memory structure is disposed in a second area of the integrated circuit that is different than the first area, and the second memory structure has second memory cells with second transistors that are separate from the first transistors. The second transistors of the second memory cells are arranged to provide an output oscillating frequency for detecting variation of performance of the first transistors of the first memory cells.

Abstract: Various implementations described herein are directed to a device having voltage generator circuitry that provides a temperature-compensated voltage. The device may include amplifier circuitry that receives the temperature-compensated voltage from the voltage generator circuitry and provides an output voltage based on the temperature-compensated voltage. The device may include voltage retention circuitry that receives the output voltage from the amplifier circuitry and provides a retention voltage to memory based on the output voltage.

Abstract: A method for identifying a logo within at least one image includes identifying an area containing the logo within the at least one image, extracting logo features from the area by analyzing image gradient vectors associated with the at least one image, and using a machine learning model to identify the logo from the extracted logo features, wherein the machine learning model is trained to identify at least one target logo based on a received image data containing the logo features.

Abstract: Methods, systems, and computer-readable media for segmentation of maintenance on distributed systems are disclosed. A data set is partitioned according to a hash function into a plurality of segments. A maintenance activity is initiated on a first segment. During the maintenance activity, a first request to perform a first action on the data set is received. Based at least in part on determining that the first request is associated with the first segment using the hash function, the first action is performed using additional processing associated with the maintenance activity. During the maintenance activity, a second request to perform a second action on the data set is received. Based at least in part on determining that the second request is associated with a second segment using the hash function, the second action is performed without the additional processing associated with the maintenance activity.

Abstract: Various implementations described herein refer to an integrated circuit having a row of bitcells that are chained together in series to operate as a ring oscillator. Each bitcell in the row of bitcells has multiple transistors that are independent of additional transistors to form the ring oscillator. The multiple transistors of each bitcell in the row of bitcells are arranged to function as an inverter.

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include first decoding circuitry that receives an address and partially decodes the address to generate a partially decoded address. The integrated circuit may include second decoding circuitry that receives the partially decoded address, generates a decoded address, and provides the decoded address to a wordline. The integrated circuit may include encoding circuitry that receives the decoded address from the wordline and encodes the decoded address to generate an encoded address. The integrated circuit may include comparing circuitry that receives the encoded address and compares the encoded address with the address to detect faults in the memory circuitry.

Abstract: Various implementations described herein are directed to an integrated circuit that has memory circuitry with a memory structure and a reference path. The integrated circuit includes performance sensing circuitry having a logic structure that is adapted to detect variation of performance of the memory structure. The integrated circuit includes power management circuitry that is coupled to the memory circuitry and the performance sensing circuitry. The power management circuitry receives a feedback signal from the performance sensing circuitry and adaptively adjusts voltage provided to the memory circuitry based on the feedback signal to affect performance of the memory structure. The memory circuitry has a logic stage that reduces signal delay in the reference path for alignment with the adaptively adjusted voltage.

Abstract: Various implementations described herein are directed to an integrated circuit that has memory circuitry with a memory structure and a reference path. The integrated circuit includes performance sensing circuitry having a logic structure that is adapted to detect variation of performance of the memory structure. The integrated circuit includes power management circuitry that is coupled to the memory circuitry and the performance sensing circuitry. The power management circuitry receives a feedback signal from the performance sensing circuitry and adaptively adjusts voltage provided to the memory circuitry based on the feedback signal to affect performance of the memory structure. The memory circuitry has a logic stage that reduces signal delay in the reference path for alignment with the adaptively adjusted voltage.

Abstract: Various implementations described herein are directed to an integrated circuit with logic circuitry having one or more components. The integrated circuit may include performance sensing circuitry that provides a performance sensing output associated with detecting variation of switching delays of the one or more components forming the logic circuitry. The integrated circuit may include transient sensing circuitry that receives the performance sensing output and provides a transient sensing output for determining stability of operating conditions of the performance sensing circuitry during one or more sampling periods. The transient sensing circuitry may use a finite state machine (FSM) to sense and classify changes in temporal behavior of the transient sensing output.

Abstract: A lottery apparatus includes a programmed computer acting as a lottery control system which controls operation of the distribution of prizes to the purchasing customers from a lottery pool. The apparatus includes a plurality of typical instant win lottery tickets having a predetermined prize result taken from the pool together with a plurality of lottery cards which do not act as lottery tickets but instead include an activation code containing no information defining a prize and an access code which is used for entry by the customer into a digital experience provided by the lottery control system by which the customer accesses game information. The system, when the code is activated, assigns the result from the pool to the code and displays to the customer on a digital experience when accessed by the access code.

Abstract: Various implementations described herein refer to an integrated circuit having a first memory structure and a second memory structure. The first memory structure is disposed in a first area of the integrated circuit, and the first memory structure has first memory cells with first transistors. The second memory structure is disposed in a second area of the integrated circuit that is different than the first area, and the second memory structure has second memory cells with second transistors that are separate from the first transistors. The second transistors of the second memory cells are arranged to provide an output oscillating frequency for detecting variation of performance of the first transistors of the first memory cells.

Abstract: Various implementations described herein refer to an integrated circuit having a row of bitcells that are chained together in series to operate as a ring oscillator. Each bitcell in the row of bitcells has multiple transistors that are independent of additional transistors to form the ring oscillator. The multiple transistors of each bitcell in the row of bitcells are arranged to function as an inverter.

Abstract: A lottery apparatus includes a programmed computer acting as a lottery control system which controls operation of the distribution of prizes to the purchasing customers from a lottery pool. The apparatus includes a plurality of typical instant win lottery tickets having a predetermined prize result taken from the pool together with a plurality of lottery cards which do not act as lottery tickets but instead include an activation code containing no information defining a prize and an access code which is used for entry by the customer into a digital experience provided by the lottery control system by which the customer accesses game information. The system, when the code is activated, assigns the result from the pool to the code and displays to the customer on a digital experience when accessed by the access code.

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include first decoding circuitry that receives an address and partially decodes the address to generate a partially decoded address. The integrated circuit may include second decoding circuitry that receives the partially decoded address, generates a decoded address, and provides the decoded address to a wordline. The integrated circuit may include encoding circuitry that receives the decoded address from the wordline and encodes the decoded address to generate an encoded address. The integrated circuit may include comparing circuitry that receives the encoded address and compares the encoded address with the address to detect faults in the memory circuitry.

Abstract: A lottery apparatus includes a programmed computer acting as a lottery control system which controls operation of the distribution of prizes to the purchasing customers from a lottery pool. The apparatus includes a plurality of typical instant win lottery tickets having a predetermined prize result taken from the pool together with a plurality of lottery cards which do not act as lottery tickets but instead include an activation code containing no information defining a prize and an access code which is used for entry by the customer into a digital experience provided by the lottery control system by which the customer accesses game information. The system, when the code is activated, assigns the result from the pool to the code and displays to the customer on a digital experience when accessed by the access code.

Abstract: A method is provided of managing awards to players in a lottery where players purchase lottery access tickets, each of which is assigned a predetermined prize in the lottery and each of which provides access to a selected one of a series of accessible video games on a computer medium. Each game has a plurality of game images in which the player can enter a selected action from a number of options based on different skill levels where the selected action can have a token value different from other options. The system displays a table to the player of an accumulation of the tokens and controls the accumulation of the tokens in order that the final prize matches the predetermined prize but may allow other awards to more skilled players. The prize must be validated using a code from the ticket and from an image in the displayed game.

Abstract: When powering-up or exiting from a sleep mode, the ramping up of various supply voltage nodes may occur at different rates. Thus, in a dual-rail memory circuit, a first voltage rail may be at voltage before a second voltage rail. Such a transient state of operation may lead to current spikes that unnecessarily draw power and introduce undesired inefficiency. An internal sleep signal generation circuit in the dual-rail memory circuit precisely controls an internal sleep signal such that the transition from off or sleep mode to operating mode is set to assure that the supply voltage nodes are close enough to the at-voltage operating level before releasing the sleep mode.