Patents by Inventor Amit K. SRIVASTAVA
Amit K. SRIVASTAVA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11874787Abstract: Methods to dynamically configure, monitor and govern PCH Chipsets in platforms as extended IO-expander(s) and associated apparatus. A multi-role PCH is provided that may be dynamically configured as a legacy PCH to facilitate booting for platforms without bootable CPUs and as IO-expanders in single-socket and multi-socket platforms. A control entity is coupled to the PCHs and is used to effect boot, reset, wake, and power management operations by exchanging handshake singles with the PCHs and providing control inputs to CPUs on the platforms. The single-socket platform configurations include a platform with a CPU with bootable logic coupled to an IO-expander and a platform with a legacy CPU coupled to a legacy PCH.Type: GrantFiled: February 13, 2020Date of Patent: January 16, 2024Assignee: Intel CorporationInventors: Amit K Srivastava, Majid Shushtarian, Anand K Enamandram, Jared W Havican, Jeffrey A Pihlman, Michael J Karas, Ramamurthy Krithivas, Christine Watnik
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Patent number: 11226922Abstract: In an embodiment, a host controller is to couple to an interconnect to which a plurality of devices may be coupled. The host controller may include: a first driver to drive first information onto the interconnect according to a bus clock signal; a first receiver to receive second information from at least one of the plurality of devices via the interconnect according to the bus clock signal; and a clock generation circuit to generate the bus clock signal having an asymmetric duty cycle. Other embodiments are described and claimed.Type: GrantFiled: December 14, 2017Date of Patent: January 18, 2022Assignee: Intel CorporationInventors: Amit K. Srivastava, Kenneth P. Foust
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Patent number: 10845407Abstract: An apparatus of a multi-chip package (MCP) of a functional safety system, comprises a processor configurable as a master chip in a master-slave arrangement with a slave chip in the MCP, and a memory coupled to the processor to store one or more infield test scan patterns. The processor includes a block to couple the master chip to the slave chip via a high-speed input/output (IO) interface to retrieve the one or more infield test scan patterns from the memory via the master chip, and to provide the one or more infield test scan patterns to the slave chip via the high-speed TO interface in response to the functional safety system entering an infield test mode.Type: GrantFiled: June 25, 2018Date of Patent: November 24, 2020Assignee: Intel CorporationInventors: Asad Azam, Amit K. Srivastava, Enrico Carrieri, Rajesh Bhaskar
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Patent number: 10732699Abstract: An apparatus is provided which comprises: a power management circuitry; and a processing circuitry comprising a processing core, wherein the power management circuitry is to: compute first voltage and frequency parameters, and transmit the first voltage and frequency parameters to the processing circuitry for operation of the processing core, and wherein in response to a detection of a fault, the power management circuitry is to: access second voltage and frequency parameters from a memory, and transmit the accessed second voltage and frequency parameters to the processing circuitry for operation of the processing core.Type: GrantFiled: February 23, 2018Date of Patent: August 4, 2020Assignee: Intel CorporationInventors: Lakshminarayana Pappu, Robert Milstrey, Amit K. Srivastava
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Publication number: 20200183872Abstract: Methods to dynamically configure, monitor and govern PCH Chipsets in platforms as extended IO-expander(s) and associated apparatus. A multi-role PCH is provided that may be dynamically configured as a legacy PCH to facilitate booting for platforms without bootable CPUs and as IO-expanders in single-socket and multi-socket platforms. A control entity is coupled to the PCHs and is used to effect boot, reset, wake, and power management operations by exchanging handshake singles with the PCHs and providing control inputs to CPUs on the platforms. The single-socket platform configurations include a platform with a CPU with bootable logic coupled to an IO-expander and a platform with a legacy CPU coupled to a legacy PCH.Type: ApplicationFiled: February 13, 2020Publication date: June 11, 2020Inventors: Amit K Srivastava, Majid Shushtarian, Anand K Enamandram, Jared W Havican, Jeffrey A Pihlman, Michael J Karas, Ramamurthy Krithivas, Christine Watnik
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Patent number: 10635611Abstract: Techniques and mechanisms for determining an orientation of a connection to an input and/or output (IO) interface of a device. In an embodiment, the device receives one or more signals, each via a respective contact of the IO interface, and identifies the orientation based a signal characteristic of the one or more signals. A communication mode of the device is then configured to accommodate the orientation. A physical arrangement of the IO interface is compatible with a signal plan of an interface type which is defined by an interface specification. The one or more signals are each of a respective signal type other than any signal type which, according to the interface specification, is to provide a basis for orientation identification. In some embodiments, the interface specification is a USB-C specification.Type: GrantFiled: January 22, 2019Date of Patent: April 28, 2020Assignee: Intel CorporationInventor: Amit K. Srivastava
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Publication number: 20190265771Abstract: An apparatus is provided which comprises: a power management circuitry; and a processing circuitry comprising a processing core, wherein the power management circuitry is to: compute first voltage and frequency parameters, and transmit the first voltage and frequency parameters to the processing circuitry for operation of the processing core, and wherein in response to a detection of a fault, the power management circuitry is to: access second voltage and frequency parameters from a memory, and transmit the accessed second voltage and frequency parameters to the processing circuitry for operation of the processing core.Type: ApplicationFiled: February 23, 2018Publication date: August 29, 2019Applicant: Intel CorporationInventors: Lakshminarayana Pappu, Robert Milstrey, Amit K. Srivastava
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Publication number: 20190049513Abstract: An apparatus of a multi-chip package (MCP) of a functional safety system, comprises a processor to be configured as a master chip in a master-slave arrangement with a slave chip in the MCP, and a memory coupled to the processor to store one or more infield test scan patterns. The processor includes a bock to couple the master chip to the slave chip via a high-speed input/output (IO) interface to retrieve the one or more infield test scan patterns from the memory via the master chip, and to provide the one or more infield test scan patterns to the slave chip via the high-speed IO interface in response to the functional safety system entering an infield test mode.Type: ApplicationFiled: June 25, 2018Publication date: February 14, 2019Applicant: Intel CorporationInventors: Asad Azam, Amit K. Srivastava, Enrico Carrieri, Rajesh Bhaskar
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Publication number: 20190042526Abstract: In an embodiment, a host controller is to couple to an interconnect to which a plurality of devices may be coupled. The host controller may include: a first driver to drive first information onto the interconnect according to a bus clock signal; a first receiver to receive second information from at least one of the plurality of devices via the interconnect according to the bus clock signal; and a clock generation circuit to generate the bus clock signal having an asymmetric duty cycle. Other embodiments are described and claimed.Type: ApplicationFiled: December 14, 2017Publication date: February 7, 2019Inventors: Amit K. Srivastava, Kenneth P. Foust
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Patent number: 8689033Abstract: A data processing device with a power supply and data signal interface circuit has a switch for connecting an external line and an internal node. The power supply and data signal interface circuit also includes a controller for applying an enabling voltage to the switch enabling the switch to supply current between the external line and the internal node in the presence of power supply to the controller and in the absence of the overvoltage condition on the external line. The power supply and data signal interface circuit also includes a voltage reduction connection from the external line for applying a control voltage to the switch in the absence of power supply to the controller. The control voltage from the voltage reduction connection limits a voltage applied to the internal node through the switch in the presence of the overvoltage condition.Type: GrantFiled: July 27, 2011Date of Patent: April 1, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Amit K. Srivastava, Parul K. Sharma
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Patent number: 8643425Abstract: An embedded system includes a level shifter circuit for generating a forward supply voltage level in a predefined range. A sense circuit senses a core supply voltage level of the embedded system and compares the sensed core supply voltage level with a predetermined minimum core supply voltage level needed to generate the forward supply voltage. A reset circuit maintains one or more input nodes and one or more internal nodes of the level shifter circuit at a predetermined voltage level when the core supply voltage level is less than the predetermined minimum core supply voltage level.Type: GrantFiled: September 19, 2011Date of Patent: February 4, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Nidhi Chaudhry, Parul K. Sharma, Amit K. Srivastava
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Publication number: 20130069707Abstract: An embedded system includes a level shifter circuit for generating a forward supply voltage level in a predefined range. A sense circuit senses a core supply voltage level of the embedded system and compares the sensed core supply voltage level with a predetermined minimum core supply voltage level needed to generate the forward supply voltage. A reset circuit maintains one or more input nodes and one or more internal nodes of the level shifter circuit at a predetermined voltage level when the core supply voltage level is less than the predetermined minimum core supply voltage level.Type: ApplicationFiled: September 19, 2011Publication date: March 21, 2013Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Nidhi CHAUDHRY, Parul K. Sharma, Amit K. Srivastava
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Publication number: 20130031398Abstract: A data processing device with a power supply and data signal interface circuit has a switch for connecting an external line and an internal node. The power supply and data signal interface circuit also includes a controller for applying an enabling voltage to the switch enabling the switch to supply current between the external line and the internal node in the presence of power supply to the controller and in the absence of the overvoltage condition on the external line. The power supply and data signal interface circuit also includes a voltage reduction connection from the external line for applying a control voltage to the switch in the absence of power supply to the controller. The control voltage from the voltage reduction connection limits a voltage applied to the internal node through the switch in the presence of the overvoltage condition.Type: ApplicationFiled: July 27, 2011Publication date: January 31, 2013Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Amit K. SRIVASTAVA, Parul K. Sharma