Patents by Inventor Amit Kumar Jain
Amit Kumar Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240119477Abstract: A digital content messaging system includes one or more media sources, a beacon (either physical or virtual), a user's smart device bound to a media device using a wallet Pass, a media device, and a processing device. The user's smart device is configured for storing a unique wallet Pass. The user's smart device is also for detecting when a user is in physical proximity of the media device, and for receiving messages from a messaging system through the stored wallet Pass. The media device is for detecting a channel that the user has selected; transmitting the channel information to a server; and receiving the media from the media sources. The processing device extracts key values from the media; matches key values from the media to a key value associated with a merchant offer; and transmits a URL of a merchant offer to the user's smart device.Type: ApplicationFiled: October 5, 2023Publication date: April 11, 2024Inventors: Jules Best, Ainsworth Spence, Jonathan H. Lewis, Amit Kumar Jain
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Patent number: 11749606Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.Type: GrantFiled: July 9, 2021Date of Patent: September 5, 2023Assignee: Intel CorporationInventors: Amit Kumar Jain, Sameer Shekhar, Chin Lee Kuan, Kevin Joseph Doran, Dong-Ho Han
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Publication number: 20230260323Abstract: The present invention provides a system and a method for biometric authentication using facial information to recognize users across different locations. Further, the system generates feature vectors based on the facial information and generates recognition metadata for the identification and categorization of users. The system utilizes a frame relay (FR) connect pipeline to provide a more economically efficient solution, enable locations with improper bandwidth, and support a large number of locations on the same hardware. The system uses an artificial intelligence (AI) engine for predicting one or more categorizations of the user based on the generated one or more recognition metadata.Type: ApplicationFiled: February 17, 2023Publication date: August 17, 2023Applicant: Jio Platforms LimitedInventors: Jitendra BHATIA, Amit Kumar JAIN, Indraksha AGARWAL, Tribhuvan Singh RATHORE
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Patent number: 11502603Abstract: Various embodiments provide a magnetic sensing scheme for a voltage regulator circuit. The voltage regulator circuit may include a first inductor (also referred to as an output inductor) coupled between a drive circuit and an output node. The voltage regulator circuit may further include a second inductor (also referred to as a sense inductor) having a first terminal coupled to the first inductor at a tap point between terminals of the first inductor. The second inductor may provide a sense voltage at a second terminal of the second inductor. A control circuit may control a state of the voltage regulator circuit based on the sense voltage to provide a regulated output voltage at the output node. Other embodiments may be described and claimed.Type: GrantFiled: June 25, 2019Date of Patent: November 15, 2022Assignee: Intel CorporationInventors: Amit Kumar Jain, Chin Lee Kuan, Sameer Shekhar
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Patent number: 11437294Abstract: Embodiments disclosed herein include electronics packages with improved thermal pathways. In an embodiment, an electronics package includes a package substrate. In an embodiment, the package substrate comprises a plurality of backside layers, a plurality of front-side layers, and a core layer between the plurality of backside layers and the plurality of front-side layers. In an embodiment, an inductor is embedded in the plurality of backside layers. In an embodiment, a plurality of bumps are formed over the front-side layers and thermally coupled to the inductor. In an embodiment, the plurality of bumps are thermally coupled to the core layer by a plurality of vias.Type: GrantFiled: August 9, 2018Date of Patent: September 6, 2022Assignee: Intel CorporationInventors: Sameer Shekhar, Amit Kumar Jain, Kaladhar Radhakrishnan, Jonathan P. Douglas, Chin Lee Kuan
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Patent number: 11380623Abstract: Embodiments herein relate to a package having a substrate with a core layer with a plurality of conductors coupling a first side of the core layer with a second side of the core layer, and a shield within the core layer that separates a first conductor of the plurality of conductors from a second conductor of the plurality of conductors where the shield is to reduce electromagnetic interference received by the second conductor that is generated by the first conductor. Embodiments may also be related to a package having a substrate with a through hole via through the substrate, where an EMI protective material is applied to a surface of the substrate that forms the via to shield an inner portion of the via.Type: GrantFiled: March 28, 2018Date of Patent: July 5, 2022Assignee: Intel CorporationInventors: Sameer Shekhar, Chin Lee Kuan, Amit Kumar Jain
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Publication number: 20220199551Abstract: Embodiments disclosed herein include electronic packages with stiffeners. In an embodiment, a stiffener for an electronic package comprises a first layer, that is conductive, and a second layer over the first layer, where the second layer is insulative. In an embodiment, the stiffener further comprises a third layer over the second layer, where the third layer is conductive. In an embodiment, the stiffener further comprises a leg attached to the third layer, where the leg extends towards the first layer and is substantially coplanar with a surface of the first layer opposite from the second layer.Type: ApplicationFiled: December 21, 2020Publication date: June 23, 2022Inventors: Amit Kumar JAIN, Sameer SHEKHAR, Telesphor KAMGAING, Chin Lee KUAN, Vivek SAXENA
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Patent number: 11175709Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a plurality of chiplets, a plurality of resources, a system thermal engine, and at least one processor. The at least one processor is configured to cause the system thermal engine to monitor the plurality of chiplets, where the plurality of chiplets are part of a multi-chip module, determine that a first chiplet from the plurality of chiplets has reached a threshold temperature, and reduce power to the first chiplet without reducing power to the other chiplets in the plurality of chiplets.Type: GrantFiled: August 26, 2019Date of Patent: November 16, 2021Assignee: Intel CorporationInventors: Amit Kumar Jain, Sameer Shekhar, Mark Carbone, Merwin M. Brown
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Publication number: 20210335712Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.Type: ApplicationFiled: July 9, 2021Publication date: October 28, 2021Applicant: Intel CorporationInventors: Amit Kumar Jain, Sameer Shekhar, Chin Lee Kuan, Kevin Joseph Doran, Dong-Ho Han
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Patent number: 11133256Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.Type: GrantFiled: June 20, 2019Date of Patent: September 28, 2021Assignee: Intel CorporationInventors: Amit Kumar Jain, Sameer Shekhar, Chin Lee Kuan, Kevin Joseph Doran, Dong-Ho Han
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Patent number: 10942900Abstract: In certain embodiments, techniques are provided (e.g., a method, a system, non-transitory computer-readable medium storing code or instructions executable by one or more processors) to provide data visualization and management services for files stored in a cloud storage system. In some embodiments, a tenant (e.g., an end user, customer, or subscriber to a cloud storage service) can view how their data is stored across data centers within a cloud storage service. A cloud file manager can analyze the tenant's data stored in the cloud storage service, and generate a data visualization interface that provides a fine grained visual representation of the tenant's data across the cloud storage service. In some embodiments, the tenant can define storage profiles and/or modify existing data storage locations dynamically through the data visualization interface. This simplifies data management for the tenants and provides increased flexibility of managing data in the cloud storage service.Type: GrantFiled: June 2, 2015Date of Patent: March 9, 2021Assignee: ORACLE INTERNATIONAL CORPORATIONInventors: Prabhakaran Rathinagiri, Chandrasekhar Atla, Amit Kumar Jain
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Patent number: 10937266Abstract: The invention provides a banknote processing machine having a power control electronics that comprises: —a low voltage monitor constructed to detect a lowering of a voltage of the power delivered by the power source below a minimum voltage; and —a power failure control circuit constructed to, in the case that a lowering of said voltage below said minimum voltage occurs, discontinue supply of power to a first group of said elements and to continue supply of power to a second group of said elements.Type: GrantFiled: December 2, 2015Date of Patent: March 2, 2021Assignee: GIESECKE+DEVRIENT CURRENCY TECHNOLOGY GMBHInventor: Amit Kumar Jain
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Publication number: 20200098674Abstract: Embodiments may relate to a semiconductor package. A conductive frame may be coupled with the semiconductor package. The conductive frame may include a first portion, a second portion, and a third portion positioned between the first portion and the second portion. The first portion may be coupled with the first side of the semiconductor package. The second portion may be coupled with the second side of the semiconductor package. The third portion may be coupled with the sidewall of the semiconductor package. Other embodiments may be described or claimed.Type: ApplicationFiled: September 26, 2018Publication date: March 26, 2020Applicant: Intel CorporationInventors: Chin Lee Kuan, Amit Kumar Jain, Sameer Shekhar
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Publication number: 20200051884Abstract: Embodiments disclosed herein include electronics packages with improved thermal pathways. In an embodiment, an electronics package includes a package substrate. In an embodiment, the package substrate comprises a plurality of backside layers, a plurality of front-side layers, and a core layer between the plurality of backside layers and the plurality of front-side layers. In an embodiment, an inductor is embedded in the plurality of backside layers. In an embodiment, a plurality of bumps are formed over the front-side layers and thermally coupled to the inductor. In an embodiment, the plurality of bumps are thermally coupled to the core layer by a plurality of vias.Type: ApplicationFiled: August 9, 2018Publication date: February 13, 2020Inventors: Sameer SHEKHAR, Amit Kumar JAIN, Kaladhar RADHAKRISHNAN, Jonathan P. DOUGLAS, Chin Lee KUAN
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Publication number: 20190384367Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a plurality of chiplets, a plurality of resources, a system thermal engine, and at least one processor. The at least one processor is configured to cause the system thermal engine to monitor the plurality of chiplets, where the plurality of chiplets are part of a multi-chip module, determine that a first chiplet from the plurality of chiplets has reached a threshold temperature, and reduce power to the first chiplet without reducing power to the other chiplets in the plurality of chiplets.Type: ApplicationFiled: August 26, 2019Publication date: December 19, 2019Applicant: Intel CorporationInventors: Amit Kumar Jain, Sameer Shekhar, Mark Carbone, Merwin M. Brown
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Publication number: 20190312513Abstract: Various embodiments provide a magnetic sensing scheme for a voltage regulator circuit. The voltage regulator circuit may include a first inductor (also referred to as an output inductor) coupled between a drive circuit and an output node. The voltage regulator circuit may further include a second inductor (also referred to as a sense inductor) having a first terminal coupled to the first inductor at a tap point between terminals of the first inductor. The second inductor may provide a sense voltage at a second terminal of the second inductor. A control circuit may control a state of the voltage regulator circuit based on the sense voltage to provide a regulated output voltage at the output node. Other embodiments may be described and claimed.Type: ApplicationFiled: June 25, 2019Publication date: October 10, 2019Inventors: Amit Kumar Jain, Chin Lee Kuan, Sameer Shekhar
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Publication number: 20190304915Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.Type: ApplicationFiled: June 20, 2019Publication date: October 3, 2019Applicant: Intel CorporationInventors: Amit Kumar Jain, Sameer Shekhar, Chin Lee Kuan, Kevin Joseph Doran, Dong-Ho Han
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Publication number: 20190304923Abstract: Embodiments herein relate to a package having a substrate with a core layer with a plurality of conductors coupling a first side of the core layer with a second side of the core layer, and a shield within the core layer that separates a first conductor of the plurality of conductors from a second conductor of the plurality of conductors where the shield is to reduce electromagnetic interference received by the second conductor that is generated by the first conductor. Embodiments may also be related to a package having a substrate with a through hole via through the substrate, where an EMI protective material is applied to a surface of the substrate that forms the via to shield an inner portion of the via.Type: ApplicationFiled: March 28, 2018Publication date: October 3, 2019Inventors: Sameer SHEKHAR, Chin Lee KUAN, Amit Kumar JAIN
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Publication number: 20170330403Abstract: The invention provides a banknote processing machine having a power control electronics that comprises: a low voltage monitor constructed to detect a lowering of a voltage of the power delivered by the power source below a minimum voltage; and a power failure control circuit constructed to, in the case that a lowering of said voltage below said minimum voltage occurs, discontinue supply of power to a first group of said elements and to continue supply of power to a second group of said elements.Type: ApplicationFiled: December 2, 2015Publication date: November 16, 2017Inventor: Amit Kumar JAIN
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Publication number: 20160357739Abstract: In certain embodiments, techniques are provided (e.g., a method, a system, non-transitory computer-readable medium storing code or instructions executable by one or more processors) to provide data visualization and management services for files stored in a cloud storage system. In some embodiments, a tenant (e.g., an end user, customer, or subscriber to a cloud storage service) can view how their data is stored across data centers within a cloud storage service. A cloud file manager can analyze the tenant's data stored in the cloud storage service, and generate a data visualization interface that provides a fine grained visual representation of the tenant's data across the cloud storage service. In some embodiments, the tenant can define storage profiles and/or modify existing data storage locations dynamically through the data visualization interface. This simplifies data management for the tenants and provides increased flexibility of managing data in the cloud storage service.Type: ApplicationFiled: June 2, 2015Publication date: December 8, 2016Inventors: Prabhakaran Rathinagiri, Chandrasekhar Atla, Amit Kumar Jain